公开(公告)号：US11956019B1

公开(公告)日：2024-04-09

申请号：US17179527

申请日：2021-02-19

Applicant: Acacia Communications, Inc.

Inventor： Ramesh K. Singh ,  Ian Dedic ,  Gavin Allen

IPC: H04B10/04 ,  H04B10/50 ,  H04B10/508 ,  H04B10/516

CPC classification number: H04B10/501 ,  H04B10/508 ,  H04B10/516

Abstract: A method, system, and apparatus for multiplexing comprising feeding a signal into a sampler, splitting a first signal into an even branch at a first set of times, splitting a second signal into an odd branch at a second set of times, feeding a switch bleed current into the first branch at the second set of time and feeding the switch bleed current into the second branch at the first set of time.

公开(公告)号：US12107544B1

公开(公告)日：2024-10-01

申请号：US16685063

申请日：2019-11-15

Applicant: Acacia Communications, Inc.

Inventor： Ian Dedic ,  Gavin Allen ,  David Enright ,  Guojun Ren

IPC: H01F27/28 ,  H03B5/12

CPC classification number: H03B5/1259 ,  H01F27/28 ,  H03B5/1268

Abstract: An apparatus comprising two inductors; wherein the two inductors are layered on top of each other in different layers of metal of a circuit; wherein each inductor of the inductor has a set of turns; wherein the current path of the two inductors is in the same direction.

公开(公告)号：US12184301B1

公开(公告)日：2024-12-31

申请号：US17373884

申请日：2021-07-13

Applicant: Acacia Communications, Inc.

Inventor： Ian Dedic ,  Gavin Allen ,  Ramesh K. Singh

IPC: H03M1/46 ,  H02M3/337 ,  H03F3/30 ,  H03M1/12 ,  H04B1/16

Abstract: An apparatus, method, and system for converting a charge to a voltage.

公开(公告)号：US11698658B1

公开(公告)日：2023-07-11

申请号：US17833306

申请日：2022-06-06

Applicant: Acacia Communications, Inc.

Inventor： Gavin Allen ,  Ian Dedic ,  Bo Yang ,  Tarun Gupta

IPC: G06F1/10 ,  H03K3/037

CPC classification number: G06F1/10 ,  H03K3/037

Abstract: A method system, and apparatus for adjusting skew in a circuit comprising feeding an input clock into a first push-pull source follower stage, feeding an inverse of an input clock bar into a first CMOS inverter stage, creating an output clock based on an equal contribution of the input clock of the first push-pull follower stage and the inverse of the input clock bar of the first CMOS invert stage, feeding the input clock bar into a first push-pull source follower stage, feeding an inverse of the input clock into a first CMOS inverter stage, and creating an output clock based on an equal contribution of the input clock bar of the first push-pull follower stage and the inverse of the input clock bar of the first CMOS invert stage.

公开(公告)号：US11543850B1

公开(公告)日：2023-01-03

申请号：US16777968

申请日：2020-01-31

Applicant: Acacia Communications, Inc.

Inventor： Ian Dedic ,  Gavin Allen ,  David Enright ,  Bo Yang ,  Tarun Gupta

IPC: G06F1/08 ,  H03B5/12 ,  H03F3/50

Abstract: An apparatus and system for a clock buffer. The clock buffer comprises a source follower, and the source follower comprises a voltage source and a resistor.

公开(公告)号：US12130656B1

公开(公告)日：2024-10-29

申请号：US18343841

申请日：2023-06-29

Applicant: Acacia Communications, Inc.

Inventor： Gavin Allen ,  Ian Dedic ,  Bo Yang ,  Taran Gupta

IPC: G06F1/10 ,  H03K3/037

CPC classification number: G06F1/10 ,  H03K3/037

Abstract: A method system, and apparatus for adjusting skew in a circuit comprising feeding an input clock into a first push-pull source follower stage, feeding an inverse of an input clock bar into a first CMOS inverter stage, creating an output clock based on an equal contribution of the input clock of the first push-pull follower stage and the inverse of the input clock bar of the first CMOS invert stage, feeding the input clock bar into a first push-pull source follower stage, feeding an inverse of the input clock into a first CMOS inverter stage, and creating an output clock based on an equal contribution of the input clock bar of the first push-pull follower stage and the inverse of the input clock bar of the first CMOS invert stage.