Trench FET with self aligned source and contact
    1.
    发明授权
    Trench FET with self aligned source and contact 有权
    具有自对准源和接触的沟槽FET

    公开(公告)号:US07301200B2

    公开(公告)日:2007-11-27

    申请号:US11376057

    申请日:2006-03-15

    IPC分类号: H01L29/76

    摘要: A trench type power MOSgated device has a plurality of spaced trenches lined with oxide and filled with conductive polysilicon. The tops of the polysilicon fillers are below the top silicon surface and are capped with a deposited oxide the top of which is flush with the top of the silicon. Source regions of short lateral extent extend into the trench walls to a depth below the top of the polysilicon. A trench termination is formed having an insulation oxide liner covered by a polysilicon layer, covered in turn by a deposited oxide.

    摘要翻译: 沟槽型功率MOS器件具有衬有氧化物并填充有导电多晶硅的多个隔开的沟槽。 多晶硅填料的顶部位于顶部硅表面之下,并用沉积的氧化物封盖,其顶部与硅的顶部齐平。 短横向范围的源区域延伸到沟槽壁中至多晶硅顶部的深度。 形成具有由多晶硅层覆盖的绝缘氧化物衬垫的沟槽端接,并且依次由被沉积的氧化物覆盖。

    Trench fet with self aligned source and contact
    2.
    发明授权
    Trench fet with self aligned source and contact 有权
    具有自对准源和接触的沟槽胎

    公开(公告)号:US07397083B2

    公开(公告)日:2008-07-08

    申请号:US11982815

    申请日:2007-11-05

    IPC分类号: H01L29/76

    摘要: A trench type power MOSgated device has a plurality of spaced trenches lined with oxide and filled with conductive polysilicon. The tops of the polysilicon fillers are below the top silicon surface and are capped with a deposited oxide the top of which is flush with the top of the silicon. Source regions of short lateral extent extend into the trench walls to a depth below the top of the polysilicon. A trench termination is formed having an insulation oxide liner covered by a polysilicon layer, covered in turn by a deposited oxide.

    摘要翻译: 沟槽型功率MOS器件具有衬有氧化物并填充有导电多晶硅的多个隔开的沟槽。 多晶硅填料的顶部位于顶部硅表面之下,并用沉积的氧化物封盖,其顶部与硅的顶部齐平。 短横向范围的源区域延伸到沟槽壁中至多晶硅顶部的深度。 形成具有由多晶硅层覆盖的绝缘氧化物衬垫的沟槽端接,并且依次由被沉积的氧化物覆盖。