公开(公告)号：US20240112297A1

公开(公告)日：2024-04-04

申请号：US17957689

申请日：2022-09-30

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Tung Chuen Kwong ,  Ying Liu ,  Akila Subramaniam

IPC: G06T1/60

CPC classification number: G06T1/60

Abstract: Methods and devices are provided for processing image data on a sub-frame portion basis using layers of a convolutional neural network. The processing device comprises memory and a processor. The processor is configured to determine, for an input tile of an image, a receptive field via backward propagation and determine a size of the input tile based on the receptive field and an amount of local memory allocated to store data for the input tile. The processor determines whether the amount of local memory allocated to store the data of the input tile and padded data for the receptive field.

公开(公告)号：US20250110538A1

公开(公告)日：2025-04-03

申请号：US18477458

申请日：2023-09-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Meeta Surendramohan Srivastav ,  Indrani Paul ,  Akila Subramaniam

IPC: G06F1/3203

Abstract: The disclosed device includes a processing component having various compute blocks, and a control circuit that switches at least one of the compute blocks from a normal voltage rail for the processing component to a second voltage rail in response to power gating a normal voltage rail. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20240111596A1

公开(公告)日：2024-04-04

申请号：US17955613

申请日：2022-09-29

Applicant: Advanced Micro Devices, Inc ,  ATI Technologies ULC

Inventor： Tung Chuen Kwong ,  King Chiu Tam ,  Akila Subramaniam

IPC: G06F9/50 ,  G06F9/54

CPC classification number: G06F9/505 ,  G06F9/542

Abstract: A scheduler of an apparatus exposes an application programming interface (API) usable to specify quality-of-service (QoS) parameters, e.g., latency, throughput, and so forth. An application, for instance, specifies the QoS parameters for a workload to be processed using a hardware compute unit. The QoS parameters are employed by the scheduler as a basis to configure a partition within a hardware compute unit. The partition is configured such that processing resources that are available via the partition to process the workload comply with the specified quality-of-service.

公开(公告)号：US20240111840A1

公开(公告)日：2024-04-04

申请号：US17957508

申请日：2022-09-30

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Akila Subramaniam ,  Ying Liu ,  Tung Chuen Kwong ,  Juanjo Noguera

IPC: G06K9/62 ,  G06N3/04

CPC classification number: G06K9/6227 ,  G06K9/6261 ,  G06N3/04

Abstract: An electronic device uses a tiling scheme selected from among a set of tiling schemes for processing instances of input data through a neural network. Each of the tiling schemes is associated with a different arrangement of portions into which instances of input data are divided for processing in the neural network. In operation, processing circuitry in the electronic device acquires information about a neural network and properties of the processing circuitry. The processing circuitry then selects a given tiling scheme from among a set of tiling schemes based on the information. The processing circuitry next processes instances of input data in the neural network using the given tiling scheme. Processing each instance of input data in the neural network includes dividing the instance of input data into portions based on the given tiling scheme, separately processing each of the portions in the neural network, and combining the respective outputs to generate an output for the instance of input data.