公开(公告)号：US20230206384A1

公开(公告)日：2023-06-29

申请号：US17563950

申请日：2021-12-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Priyadarshi Sharma ,  Anshuman Mittal ,  Saurabh Sharma

IPC: G06T1/60 ,  G06F12/0891 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06F12/0891 ,  G06T1/20 ,  G06F2212/455

Abstract: Systems, apparatuses, and methods for performing dead surface invalidation are disclosed. An application sends draw call commands to a graphics processing unit (GPU) via a driver, with the draw call commands rendering to surfaces. After it is determined that a given surface will no longer be accessed by subsequent draw calls, the application sends a surface invalidation command for the given surface to a command processor of the GPU. After the command processor receives the surface invalidation command, the command processor waits for a shader engine to send a draw call completion message for a last draw call to access the given surface. Once the command processor receives the draw call completion message, the command processor sends a surface invalidation command to a cache to invalidate cache lines for the given surface to free up space in the cache for other data.

公开(公告)号：US20240320034A1

公开(公告)日：2024-09-26

申请号：US18189995

申请日：2023-03-24

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Josip Popovic ,  Anshuman Mittal

IPC: G06F9/48 ,  G06F9/50

CPC classification number: G06F9/4881 ,  G06F9/4893 ,  G06F9/5038

Abstract: An apparatus and method for efficiently managing voltage droop among replicated compute circuits of an integrated circuit. In various implementations, an integrated circuit includes multiple, replicated compute circuits, each including circuitry to process tasks grouped into a work block. When a scheduling window has begun, the scheduler determines a value for a threshold number of idle compute circuits that can be simultaneously activated based on one or more of a number of active compute circuits, an operating clock frequency, a measured operating temperature, a number of pending work blocks, and an application identifier. If the scheduler determines that there is a count of idle compute circuits that is equal to or greater than the threshold number of idle compute circuits, then the scheduler limits the number of idle compute circuits that can be activated at one time to the threshold number.

公开(公告)号：US20250004516A1

公开(公告)日：2025-01-02

申请号：US18346070

申请日：2023-06-30

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Josip Popovic ,  Anshuman Mittal ,  Kellie Marks

IPC: G06F1/26

Abstract: An apparatus and method for efficiently managing voltage droop among replicated compute circuits of an integrated circuit. In various implementations, an integrated circuit includes multiple, replicated compute circuits, each with the circuitry of multiple lanes of execution. Control circuitry of the integrated circuit identifies, early in execution pipelines, groups of instructions to be executed by a corresponding compute circuit, and generates a total power consumption estimate for the groups. The control circuitry maintains N previous total power consumption estimates, and stores the N power consumption estimates in staging circuitry referred to as an “instruction history pipeline.” If any differences between total power consumption estimates of different stages of the instruction history pipeline exceeds a corresponding threshold, then the control circuitry reduces, late in the execution pipeline, the rate of instruction execution of computation lanes of a corresponding compute circuit.

公开(公告)号：US12033239B2

公开(公告)日：2024-07-09

申请号：US17563950

申请日：2021-12-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Priyadarshi Sharma ,  Anshuman Mittal ,  Saurabh Sharma

IPC: G06T1/20 ,  G06F12/0891 ,  G06T1/60

CPC classification number: G06T1/60 ,  G06F12/0891 ,  G06T1/20 ,  G06F2212/455

Abstract: Systems, apparatuses, and methods for performing dead surface invalidation are disclosed. An application sends draw call commands to a graphics processing unit (GPU) via a driver, with the draw call commands rendering to surfaces. After it is determined that a given surface will no longer be accessed by subsequent draw calls, the application sends a surface invalidation command for the given surface to a command processor of the GPU. After the command processor receives the surface invalidation command, the command processor waits for a shader engine to send a draw call completion message for a last draw call to access the given surface. Once the command processor receives the draw call completion message, the command processor sends a surface invalidation command to a cache to invalidate cache lines for the given surface to free up space in the cache for other data.

公开(公告)号：US20240085970A1

公开(公告)日：2024-03-14

申请号：US17932155

申请日：2022-09-14

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Josip Popovic ,  Anshuman Mittal

IPC: G06F1/3237 ,  G06F9/48

CPC classification number: G06F1/3237 ,  G06F9/4843

Abstract: An apparatus and method for efficient power management of multiple integrated circuits. In various implementations, a computing system includes first partition and a second partition. The second partition includes video pre-processing circuitry that identifies regions of a video frame to be presented on a screen or monitor that don't change or regions that can have one or more of resolution and color accuracy be below a threshold. The first partition includes a parallel data processor with one or more compute units, each with multiple lanes of execution. Based on the identified regions, the first partition generates an execution mask indicating which lanes of the compute units are inactive. The parallel data processor copies result data from the active lanes to outputs of the inactive lanes.