公开(公告)号：US20210141740A1

公开(公告)日：2021-05-13

申请号：US16683142

申请日：2019-11-13

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kalamatianos ,  Apostolos Kokolis ,  Shrikanth Ganapathy

IPC: G06F12/126 ,  G06F12/1027 ,  G06F12/0804

Abstract: A technique for accessing a memory having a high latency portion and a low latency portion is provided. The technique includes detecting a promotion trigger to promote data from the high latency portion to the low latency portion, in response to the promotion trigger, copying cache lines associated with the promotion trigger from the high latency portion to the low latency portion, and in response to a read request, providing data from either or both of the high latency portion or the low latency portion, based on a state associated with data in the high latency portion and the low latency portion.