公开(公告)号：US20240121192A1

公开(公告)日：2024-04-11

申请号：US18194311

申请日：2023-03-31

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Ashwini Chandrashekhara Holla ,  Indrani Paul ,  Alexander J. Branover ,  Carlos Javier Moreira

IPC: H04L47/125 ,  H04L47/11

CPC classification number: H04L47/125 ,  H04L47/11

Abstract: The disclosed device for packet coalescing includes detecting a trigger condition for initiating packet coalescing of packet traffic and sending, to an endpoint device, a notification to start packet coalescing. The device can observe a status in response to starting the packet coalescing and report a performance of the packet coalescing. A system can include a controller that detects a trigger condition for packet coalescing and notifies an endpoint device via a notification register. The controller can read a status register to report, based on the read status, a packet coalescing performance. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20230205248A1

公开(公告)日：2023-06-29

申请号：US17560823

申请日：2021-12-23

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Meeta Surendramohan Srivastav ,  Ashwini Chandrashekhara Holla ,  Alex Sabino Duenas ,  Xinzhe Li ,  Michael John Austin ,  Indrani Paul ,  Sriram Sambamurthy

IPC: G05F1/66 ,  G06F1/28

CPC classification number: G05F1/66 ,  G06F1/28

Abstract: An electronic device includes an accelerated processing unit (APU) and multiple elements. The APU performs operations for a platform boost and throttle (PBT) controller. For the operations, the APU receives a platform electrical power limit, the platform electrical power limit being a limit on a total electrical power allowed to be consumed by a group of the elements at a given time. The APU then determines a present platform electrical power consumption. The APU next adjusts one or more operating parameters for specified elements from among the group of elements to control electrical power consumption by the specified elements based on a relationship between the present platform electrical power consumption and the platform electrical power limit.

公开(公告)号：US11714442B2

公开(公告)日：2023-08-01

申请号：US17560823

申请日：2021-12-23

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Meeta Surendramohan Srivastav ,  Ashwini Chandrashekhara Holla ,  Alex Sabino Duenas ,  Xinzhe Li ,  Michael John Austin ,  Indrani Paul ,  Sriram Sambamurthy

IPC: G06F1/28 ,  G05F1/66

CPC classification number: G05F1/66 ,  G06F1/28

Abstract: An electronic device includes an accelerated processing unit (APU) and multiple elements. The APU performs operations for a platform boost and throttle (PBT) controller. For the operations, the APU receives a platform electrical power limit, the platform electrical power limit being a limit on a total electrical power allowed to be consumed by a group of the elements at a given time. The APU then determines a present platform electrical power consumption. The APU next adjusts one or more operating parameters for specified elements from among the group of elements to control electrical power consumption by the specified elements based on a relationship between the present platform electrical power consumption and the platform electrical power limit.

公开(公告)号：US20240370077A1

公开(公告)日：2024-11-07

申请号：US18312522

申请日：2023-05-04

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Paul A. Mackey ,  Michael John Austin ,  Xinzhe Li ,  Alexander S. Duenas ,  Davis Matthew Castillo ,  Ashwini Chandrashekhara Holla

IPC: G06F1/3296

Abstract: A computing device is provided which comprises memory and a processor in communication with the memory. The processor is configured to autonomously acquire input parameter values, comprising one of monitored device input parameter values from a component of the computing device and monitored user input parameter values. The processor is also configured to select, from a plurality of modes of operation, a mode of operation comprising parameter settings which are determined based on the acquired input parameter values, each of the plurality of modes of operation comprising different parameter settings configured to control the computing device to operate at a different level of performance. The processor is also configured to control operation of the computing device by tuning the parameter settings of the computing device according to the selected mode of operation comprising the determined parameter settings.

公开(公告)号：US20230195666A1

公开(公告)日：2023-06-22

申请号：US17559984

申请日：2021-12-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander Sabino Duenas ,  Ashwini Chandrashekhara Holla ,  I-Cheng Chen ,  Xinzhe Li

IPC: G06F13/36 ,  G06F21/62

CPC classification number: G06F13/36 ,  G06F21/6218

Abstract: An electronic device includes a memory and a processor. The processor acquires a platform management profile, the platform management profile including information defining one or more platform management policies. The processor provides the platform management profile to platform management drivers executing on one or more electronic devices, the platform management profile being configured so that each of the platform management drivers can extract the one or more platform management policies from the platform management profile and use the one or more platform management policies for controlling operating states of elements (e.g., functional blocks, devices, etc.) of the respective electronic device.

公开(公告)号：US20240004453A1

公开(公告)日：2024-01-04

申请号：US17854858

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Ashwini Chandrashekhara Holla ,  Alexander S. Duenas ,  Xinzhe Li ,  Indrani Paul ,  Karthik Rao

IPC: G06F1/324

CPC classification number: G06F1/324

Abstract: Methods and systems are disclosed for managing the power consumed by cores of a system on chip (SoC). Techniques disclosed include obtaining application information that is indicative of an application being executed on the cores, detecting a workload associated with the application, and limiting one or more operating frequencies of the cores responsive to the detection of the workload. Techniques disclosed also include profiling the detected workload and limiting the one or more operating frequencies of the cores based on the profiling.

公开(公告)号：US20230418664A1

公开(公告)日：2023-12-28

申请号：US17846593

申请日：2022-06-22

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Donny Yi ,  Indrani Paul ,  Ashwini Chandrashekhara Holla

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/50 ,  G06F9/30

CPC classification number: G06F9/4881 ,  G06F9/3836 ,  G06F9/5038 ,  G06F9/5044 ,  G06F9/30079

Abstract: An apparatus and method for efficiently scheduling tasks in a dynamic manner to multiple cores that support a heterogeneous computing architecture. A computing system includes multiple cores with at least two cores being capable of executing instructions of a same instruction set architecture (ISA), and therefore, are architecturally compatible. In an implementation, each of the at least two cores is a general-purpose central processing unit (CPU) core capable of executing instructions of a same ISA. However, the throughput and the power consumption greatly differ between the at least two cores based on their hardware designs. An operating system scheduler assigns a thread to a first core, and the first core measures thread dynamic behavior of the thread over a time interval. Based on the thread dynamic behavior, the scheduler reassigns the thread to a second core different from the first core.