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公开(公告)号：US20240235376A1
公开(公告)日：2024-07-11
申请号：US18478485
申请日：2023-09-29
发明人： David King Wai Li , Amanullah Samit , Indrani Paul , Meeta Surendramohan Srivastav , Sriram Sambamurthy
摘要： The disclosed voltage regulator circuit includes a capacitor bank configured for a first voltage step corresponding to a voltage undershoot, and a shunt circuit configured for a second voltage step exceeding the first voltage step. Various other methods, systems, and computer-readable media are also disclosed.
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公开(公告)号：US11714442B2
公开(公告)日：2023-08-01
申请号：US17560823
申请日：2021-12-23
发明人： Meeta Surendramohan Srivastav , Ashwini Chandrashekhara Holla , Alex Sabino Duenas , Xinzhe Li , Michael John Austin , Indrani Paul , Sriram Sambamurthy
摘要： An electronic device includes an accelerated processing unit (APU) and multiple elements. The APU performs operations for a platform boost and throttle (PBT) controller. For the operations, the APU receives a platform electrical power limit, the platform electrical power limit being a limit on a total electrical power allowed to be consumed by a group of the elements at a given time. The APU then determines a present platform electrical power consumption. The APU next adjusts one or more operating parameters for specified elements from among the group of elements to control electrical power consumption by the specified elements based on a relationship between the present platform electrical power consumption and the platform electrical power limit.
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公开(公告)号：US11703930B2
公开(公告)日：2023-07-18
申请号：US17381664
申请日：2021-07-21
发明人： Indrani Paul , Sriram Sambamurthy , Larry David Hewitt , Kevin M. Lepak , Samuel D. Naffziger , Adam Neil Calder Clark , Aaron Joseph Grenat , Steven Frederick Liepe , Sandhya Shyamasundar , Wonje Choi , Dana Glenn Lewis , Leonardo de Paula Rosa Piga
IPC分类号： G06F1/00 , G06F1/3225 , G06F1/3234 , G06F1/3203 , G06F1/26
CPC分类号： G06F1/3225 , G06F1/3275 , G06F1/26 , G06F1/3203
摘要： Platform power management includes boosting performance in a platform power boost mode or restricting performance to keep a power or temperature under a desired threshold in a platform power cap mode. Platform power management exploits the mutually exclusive nature of activities and the associated headroom created in a temperature and/or power budget of a server platform to boost performance of a particular component while also keeping temperature and/or power below a threshold or budget.
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公开(公告)号：US20230088994A1
公开(公告)日：2023-03-23
申请号：US17993562
申请日：2022-11-23
发明人： Karthik RAO , Indrani Paul , Donny YI , Oleksandr KHODORKOVSKY , Leonardo DE PAULA ROSA PIGA , Wonje CHOI , Dana G. LEWIS , Sriram SAMBAMURTHY
IPC分类号： G06F1/3287
摘要： An apparatus includes a processor, a sleep state duration prediction module, and a system management unit. The sleep state duration prediction module is configured to predict a sleep state duration for component of the processing device. The system management unit is to transition the component into a sleep state selected from a plurality of sleep states based on a comparison of the predicted sleep state duration to at least one duration threshold. Each sleep state of the plurality of sleep states is a lower power state than a previous sleep state of the plurality of sleep states.
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公开(公告)号：US11054883B2
公开(公告)日：2021-07-06
申请号：US16011476
申请日：2018-06-18
IPC分类号： G06F1/324
摘要： A power management algorithm framework proposes: 1) a Quality-of-Service (QoS) metric for throughput-based workloads; 2) heuristics to differentiate between throughput and latency sensitive workloads; and 3) an algorithm that combines the heuristic and QoS metric to determine target frequency for minimizing idle time and improving power efficiency without any performance degradation. A management algorithm framework enables optimizing power efficiency in server-class throughput-based workloads while still providing desired performance for latency sensitive workloads. The power savings are achieved by identifying workloads in which one or more cores can be run at a lower frequency (and consequently lower power) without a significant negative performance impact.
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公开(公告)号：US20230280819A1
公开(公告)日：2023-09-07
申请号：US18316865
申请日：2023-05-12
发明人： Alexander J. Branover , Christopher T. Weaver , Benjamin Tsien , Indrani Paul , Mihir Shaileshbhai Doctor , Thomas J. Gibney , John P. Petry , Dennis Au , Oswin Hall
IPC分类号： G06F1/3234 , G06F1/3209
CPC分类号： G06F1/3265 , G06F1/3209 , G06F1/3275
摘要： A method and system for operating in a single display mode operation and a dual pipe mode of operation is disclosed. The method and system includes operating in a dual pipe mode of operation in which each display pipe transmits data from a respective buffer to an associated display. The method and system further includes operating in a single display mode of operation in which one display pipe transmits data from a plurality of buffers to an associated display.
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公开(公告)号：US11662798B2
公开(公告)日：2023-05-30
申请号：US17390479
申请日：2021-07-30
发明人： Alexander J. Branover , Christopher T. Weaver , Benjamin Tsien , Indrani Paul , Mihir Shaileshbhai Doctor , Thomas J. Gibney , John P. Petry , Dennis Au , Oswin Hall
IPC分类号： G06F1/32 , G06F1/3234 , G06F1/3209
CPC分类号： G06F1/3265 , G06F1/3209 , G06F1/3275
摘要： A disclosed technique includes transmitting data in a first buffer associated with a first display pipe to a first display associated with the first display pipe; transmitting data in a second buffer associated with a second display pipe to the first display; requesting wake-up of a memory; and refilling one or both of the first buffer and the second buffer from the memory.
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公开(公告)号：US20230036191A1
公开(公告)日：2023-02-02
申请号：US17390479
申请日：2021-07-30
发明人： Alexander J. Branover , Christopher T. Weaver , Benjamin Tsien , Indrani Paul , Mihir Shaileshbhai Doctor , Thomas J. Gibney , John P. Petry , Dennis Au , Oswin Hall
IPC分类号： G06F1/3234 , G06F1/3209
摘要： A disclosed technique includes transmitting data in a first buffer associated with a first display pipe to a first display associated with the first display pipe; transmitting data in a second buffer associated with a second display pipe to the first display; requesting wake-up of a memory; and refilling one or both of the first buffer and the second buffer from the memory.
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公开(公告)号：US20240121192A1
公开(公告)日：2024-04-11
申请号：US18194311
申请日：2023-03-31
IPC分类号： H04L47/125 , H04L47/11
CPC分类号： H04L47/125 , H04L47/11
摘要： The disclosed device for packet coalescing includes detecting a trigger condition for initiating packet coalescing of packet traffic and sending, to an endpoint device, a notification to start packet coalescing. The device can observe a status in response to starting the packet coalescing and report a performance of the packet coalescing. A system can include a controller that detects a trigger condition for packet coalescing and notifies an endpoint device via a notification register. The controller can read a status register to report, based on the read status, a packet coalescing performance. Various other methods, systems, and computer-readable media are also disclosed.
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10.发明公开公开(公告)号：US20230205248A1
公开(公告)日：2023-06-29
申请号：US17560823
申请日：2021-12-23
发明人： Meeta Surendramohan Srivastav , Ashwini Chandrashekhara Holla , Alex Sabino Duenas , Xinzhe Li , Michael John Austin , Indrani Paul , Sriram Sambamurthy
摘要： An electronic device includes an accelerated processing unit (APU) and multiple elements. The APU performs operations for a platform boost and throttle (PBT) controller. For the operations, the APU receives a platform electrical power limit, the platform electrical power limit being a limit on a total electrical power allowed to be consumed by a group of the elements at a given time. The APU then determines a present platform electrical power consumption. The APU next adjusts one or more operating parameters for specified elements from among the group of elements to control electrical power consumption by the specified elements based on a relationship between the present platform electrical power consumption and the platform electrical power limit.
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