公开(公告)号：US20140136819A1

公开(公告)日：2014-05-15

申请号：US13673350

申请日：2012-11-09

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Ganesh Venkataramanan ,  Debjit Das Sarma ,  Betty A. McDaniel ,  Gregory W. Smaus ,  Francesco Spadini

IPC: G06F9/30

CPC classification number: G06F9/3857 ,  G06F9/30043 ,  G06F9/3826 ,  G06F9/384

Abstract: A processor includes a physical register file having physical registers and an execution unit to perform an arithmetic operation to generate a result mapped to a physical register, wherein the processor delays a write of the result to the physical register file until the result is qualified as valid. A method includes mapping the same physical register both to store load data of a load-execute operation and to subsequently store a result of an arithmetic operation of the load-execute operation, and writing the load data into the physical register. The method further includes, in a first clock cycle, executing the arithmetic operation to generate the result, and, in a second clock cycle, providing the result as a source operand for a dependent operation. The method includes, in a third clock cycle, enabling a write of the result to the physical register file responsive to the result qualifying as valid.

Abstract translation: 处理器包括具有物理寄存器的物理寄存器文件和用于执行算术运算以产生映射到物理寄存器的结果的执行单元，其中处理器将结果的写入延迟到物理寄存器堆，直到结果合格为有效 。 一种方法包括将相同的物理寄存器映射到存储加载执行操作的负载数据，并随后存储加载执行操作的算术运算的结果，并将加载数据写入物理寄存器。 该方法还包括在第一时钟周期中执行算术运算以产生结果，并且在第二时钟周期中，将结果提供为依赖操作的源操作数。 该方法包括在第三时钟周期中，使结果符合有效的结果写入物理寄存器文件。

公开(公告)号：US09582286B2

公开(公告)日：2017-02-28

申请号：US13673350

申请日：2012-11-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Ganesh Venkataramanan ,  Debjit Das Sarma ,  Betty A. McDaniel ,  Gregory W. Smaus ,  Francesco Spadini

IPC: G06F9/30 ,  G06F9/44 ,  G06F9/38

CPC classification number: G06F9/3857 ,  G06F9/30043 ,  G06F9/3826 ,  G06F9/384

Abstract: A processor includes a physical register file having physical registers and an execution unit to perform an arithmetic operation to generate a result mapped to a physical register, wherein the processor delays a write of the result to the physical register file until the result is qualified as valid. A method includes mapping the same physical register both to store load data of a load-execute operation and to subsequently store a result of an arithmetic operation of the load-execute operation, and writing the load data into the physical register. The method further includes, in a first clock cycle, executing the arithmetic operation to generate the result, and, in a second clock cycle, providing the result as a source operand for a dependent operation. The method includes, in a third clock cycle, enabling a write of the result to the physical register file responsive to the result qualifying as valid.

Abstract translation: 处理器包括具有物理寄存器的物理寄存器文件和用于执行算术运算以产生映射到物理寄存器的结果的执行单元，其中处理器将结果的写入延迟到物理寄存器堆，直到结果合格为有效 。 一种方法包括将相同的物理寄存器映射到存储加载执行操作的负载数据，并随后存储加载执行操作的算术运算的结果，并将加载数据写入物理寄存器。 该方法还包括在第一时钟周期中执行算术运算以产生结果，并且在第二时钟周期中，将结果提供为依赖操作的源操作数。 该方法包括在第三时钟周期中，使结果符合有效的结果写入物理寄存器文件。