公开(公告)号：US09727340B2

公开(公告)日：2017-08-08

申请号：US13944302

申请日：2013-07-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael Achenbach ,  Teik Tan ,  Gregory W. Smaus ,  Ganesh Venkataramanan ,  Emil Talpes

IPC: G06F9/38

CPC classification number: G06F9/3836 ,  G06F9/3838 ,  G06F9/384

Abstract: The present invention provides a method and apparatus for scheduling based on tags of different types. Some embodiments of the method include broadcasting a first tag to entries in a queue of a scheduler. The first tag is broadcast in response to a first instruction associated with a first entry in the queue being picked for execution. The first tag includes information identifying the first entry and information indicating a type of the first tag. Some embodiments of the method also include marking at least one second entry in the queue is ready to be picked for execution in response to at least one second tag associated with at least one second entry in the queue matching the first tag.

公开(公告)号：US20140136819A1

公开(公告)日：2014-05-15

申请号：US13673350

申请日：2012-11-09

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Ganesh Venkataramanan ,  Debjit Das Sarma ,  Betty A. McDaniel ,  Gregory W. Smaus ,  Francesco Spadini

IPC: G06F9/30

CPC classification number: G06F9/3857 ,  G06F9/30043 ,  G06F9/3826 ,  G06F9/384

Abstract: A processor includes a physical register file having physical registers and an execution unit to perform an arithmetic operation to generate a result mapped to a physical register, wherein the processor delays a write of the result to the physical register file until the result is qualified as valid. A method includes mapping the same physical register both to store load data of a load-execute operation and to subsequently store a result of an arithmetic operation of the load-execute operation, and writing the load data into the physical register. The method further includes, in a first clock cycle, executing the arithmetic operation to generate the result, and, in a second clock cycle, providing the result as a source operand for a dependent operation. The method includes, in a third clock cycle, enabling a write of the result to the physical register file responsive to the result qualifying as valid.

Abstract translation: 处理器包括具有物理寄存器的物理寄存器文件和用于执行算术运算以产生映射到物理寄存器的结果的执行单元，其中处理器将结果的写入延迟到物理寄存器堆，直到结果合格为有效 。 一种方法包括将相同的物理寄存器映射到存储加载执行操作的负载数据，并随后存储加载执行操作的算术运算的结果，并将加载数据写入物理寄存器。 该方法还包括在第一时钟周期中执行算术运算以产生结果，并且在第二时钟周期中，将结果提供为依赖操作的源操作数。 该方法包括在第三时钟周期中，使结果符合有效的结果写入物理寄存器文件。

公开(公告)号：US09489206B2

公开(公告)日：2016-11-08

申请号：US13943264

申请日：2013-07-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Francesco Spadini ,  Michael Achenbach ,  Emil Talpes ,  Ganesh Venkataramanan

IPC: G06F9/00 ,  G06F9/38

CPC classification number: G06F9/3836 ,  G06F9/30043 ,  G06F9/3826 ,  G06F9/3842 ,  G06F9/3861

Abstract: A method includes suppressing execution of at least one dependent instruction of a first instruction by a processor responsive to an invalid status of an ancestor load instruction associated with the first instruction. A processor includes an instruction pipeline having an execution unit to execute instructions, a load store unit for retrieving data from a memory hierarchy, and a scheduler unit. The scheduler unit selects for execution in the execution unit a first load instruction having at least one dependent instruction linked to the first load instruction for data forwarding from the load store unit and suppresses execution of a second dependent instruction of the first dependent instruction responsive to an invalid status of the first load instruction.

Abstract translation: 一种方法包括响应于与第一指令相关联的祖先加载指令的无效状态来抑制由处理器执行的第一指令的至少一个依赖指令的执行。 处理器包括具有执行指令的执行单元的指令流水线，用于从存储器层次中检索数据的加载存储单元和调度器单元。 调度器单元在执行单元中选择执行具有至少一个依赖指令的第一加载指令，该至少一个依赖指令与来自加载存储单元的数据转发的第一加载指令相关联，并且响应于第一加载指令执行第一依赖指令 第一次加载指令的无效状态。

公开(公告)号：US20150026436A1

公开(公告)日：2015-01-22

申请号：US13944302

申请日：2013-07-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Michael Achenbach ,  Teik Tan ,  Gregory W. Smaus ,  Ganesh Venkataramanan ,  Emil Talpes

IPC: G06F9/38

CPC classification number: G06F9/3836 ,  G06F9/3838 ,  G06F9/384

Abstract: The present invention provides a method and apparatus for scheduling based on tags of different types. Some embodiments of the method include broadcasting a first tag to entries in a queue of a scheduler. The first tag is broadcast in response to a first instruction associated with a first entry in the queue being picked for execution. The first tag includes information identifying the first entry and information indicating a type of the first tag. Some embodiments of the method also include marking at least one second entry in the queue is ready to be picked for execution in response to at least one second tag associated with at least one second entry in the queue matching the first tag.

Abstract translation: 本发明提供一种基于不同类型的标签进行调度的方法和装置。 该方法的一些实施例包括将第一标签广播到调度器的队列中的条目。 响应于与正被挑选执行的队列中的第一条目相关联的第一指令来广播第一标签。 第一标签包括识别第一条目的信息和指示第一标签的类型的信息。 该方法的一些实施例还包括标记队列中的至少一个第二条目准备好被选择以响应于与匹配第一标签的队列中的至少一个第二条目相关联的至少一个第二标签来执行。

公开(公告)号：US09582286B2

公开(公告)日：2017-02-28

申请号：US13673350

申请日：2012-11-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Ganesh Venkataramanan ,  Debjit Das Sarma ,  Betty A. McDaniel ,  Gregory W. Smaus ,  Francesco Spadini

IPC: G06F9/30 ,  G06F9/44 ,  G06F9/38

CPC classification number: G06F9/3857 ,  G06F9/30043 ,  G06F9/3826 ,  G06F9/384

Abstract: A processor includes a physical register file having physical registers and an execution unit to perform an arithmetic operation to generate a result mapped to a physical register, wherein the processor delays a write of the result to the physical register file until the result is qualified as valid. A method includes mapping the same physical register both to store load data of a load-execute operation and to subsequently store a result of an arithmetic operation of the load-execute operation, and writing the load data into the physical register. The method further includes, in a first clock cycle, executing the arithmetic operation to generate the result, and, in a second clock cycle, providing the result as a source operand for a dependent operation. The method includes, in a third clock cycle, enabling a write of the result to the physical register file responsive to the result qualifying as valid.

Abstract translation: 处理器包括具有物理寄存器的物理寄存器文件和用于执行算术运算以产生映射到物理寄存器的结果的执行单元，其中处理器将结果的写入延迟到物理寄存器堆，直到结果合格为有效 。 一种方法包括将相同的物理寄存器映射到存储加载执行操作的负载数据，并随后存储加载执行操作的算术运算的结果，并将加载数据写入物理寄存器。 该方法还包括在第一时钟周期中执行算术运算以产生结果，并且在第二时钟周期中，将结果提供为依赖操作的源操作数。 该方法包括在第三时钟周期中，使结果符合有效的结果写入物理寄存器文件。

公开(公告)号：US09483273B2

公开(公告)日：2016-11-01

申请号：US13943310

申请日：2013-07-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Francesco Spadini ,  Michael Achenbach ,  Emil Talpes ,  Ganesh Venkataramanan

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3836 ,  G06F9/30043 ,  G06F9/3842

Abstract: A method includes suppressing execution of an operation portion of a load-operation instruction in a processor responsive to an invalid status of a load portion of load-operation instruction. A processor includes an instruction pipeline including an execution unit operable to execute instructions and a scheduler unit. The scheduler unit includes a scheduler queue and is operable to store a load-operation in the scheduler queue. The load-operation instruction includes a load portion and an operation portion. The scheduler unit schedules the load portion for execution in the execution unit, marks the operation portion in the scheduler queue as eligible for execution responsive to scheduling the load portion, receives an indication of an invalid status of the load portion, and suppresses execution of the operation portion responsive to the indication of the invalid status.

Abstract translation: 一种方法包括响应于负载操作指令的负载部分的无效状态来抑制处理器中的负载操作指令的操作部分的执行。 处理器包括指令流水线，该指令流水线包括可操作以执行指令的执行单元和调度器单元。 调度器单元包括调度器队列，并且可操作以在调度器队列中存储加载操作。 负载操作指令包括负载部分和操作部分。 调度器单元调度负载部分以在执行单元中执行，将响应于调度负载部分的调度器队列中的操作部分标记为符合执行条件，接收负载部分的无效状态的指示，并且抑制 操作部分响应于无效状态的指示。

公开(公告)号：US20150026686A1

公开(公告)日：2015-01-22

申请号：US13943310

申请日：2013-07-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Francesco Spadini ,  Michael Achenbach ,  Emil Talpes ,  Ganesh Venkataramanan

IPC: G06F9/48 ,  G06F9/38

CPC classification number: G06F9/3836 ,  G06F9/30043 ,  G06F9/3842

Abstract: A method includes suppressing execution of an operation portion of a load-operation instruction in a processor responsive to an invalid status of a load portion of load-operation instruction. A processor includes an instruction pipeline including an execution unit operable to execute instructions and a scheduler unit. The scheduler unit includes a scheduler queue and is operable to store a load-operation in the scheduler queue. The load-operation instruction includes a load portion and an operation portion. The scheduler unit schedules the load portion for execution in the execution unit, marks the operation portion in the scheduler queue as eligible for execution responsive to scheduling the load portion, receives an indication of an invalid status of the load portion, and suppresses execution of the operation portion responsive to the indication of the invalid status.

Abstract translation: 一种方法包括响应于负载操作指令的负载部分的无效状态来抑制处理器中的负载操作指令的操作部分的执行。 处理器包括指令流水线，该指令流水线包括可操作以执行指令的执行单元和调度器单元。 调度器单元包括调度器队列，并且可操作以在调度器队列中存储加载操作。 负载操作指令包括负载部分和操作部分。 调度器单元调度负载部分以在执行单元中执行，将响应于调度负载部分的调度器队列中的操作部分标记为符合执行条件，接收负载部分的无效状态的指示，并且抑制 操作部分响应于无效状态的指示。

公开(公告)号：US20150026685A1

公开(公告)日：2015-01-22

申请号：US13943264

申请日：2013-07-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Francesco Spadini ,  Michael Achenbach ,  Emil Talpes ,  Ganesh Venkataramanan

IPC: G06F9/48 ,  G06F9/38

CPC classification number: G06F9/3836 ,  G06F9/30043 ,  G06F9/3826 ,  G06F9/3842 ,  G06F9/3861

Abstract: A method includes suppressing execution of at least one dependent instruction of a first instruction by a processor responsive to an invalid status of an ancestor load instruction associated with the first instruction. A processor includes an instruction pipeline having an execution unit to execute instructions, a load store unit for retrieving data from a memory hierarchy, and a scheduler unit. The scheduler unit selects for execution in the execution unit a first load instruction having at least one dependent instruction linked to the first load instruction for data forwarding from the load store unit and suppresses execution of a second dependent instruction of the first dependent instruction responsive to an invalid status of the first load instruction.

Abstract translation: 一种方法包括响应于与第一指令相关联的祖先加载指令的无效状态来抑制由处理器执行的第一指令的至少一个依赖指令的执行。 处理器包括具有执行指令的执行单元的指令流水线，用于从存储器层次中检索数据的加载存储单元和调度器单元。 调度器单元在执行单元中选择执行具有至少一个依赖指令的第一加载指令，该至少一个依赖指令与来自加载存储单元的数据转发的第一加载指令相关联，并且响应于第一加载指令执行第一依赖指令 第一次加载指令的无效状态。