公开(公告)号：US20190196839A1

公开(公告)日：2019-06-27

申请号：US15853169

申请日：2017-12-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Christopher Spence Oliver ,  Hanbing Liu ,  Christopher James Burke ,  Michael D. Achenbach

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3855 ,  G06F9/3005

Abstract: A system and method for increasing address generation operations per cycle is described. In particular, a unified address generation scheduler queue (AGSQ) is a single queue structure which is accessed by first and second pickers in a picking cycle. Picking collisions are avoided by assigning a first set of entries to the first picker and a second set of entries to the second picker. The unified AGSQ uses a shifting, collapsing queue structure to shift other micro-operations into issued entries, which in turn collapses the queue and re-balances the unified AGSQ. A second level and delayed picker picks a third micro-operation that is ready for issue in the picking cycle. The third micro-operation is picked from the remaining entries across the first set of entries and the second set of entries. The third micro-operation issues in a next picking cycle.