公开(公告)号：US20190310845A1

公开(公告)日：2019-10-10

申请号：US16450897

申请日：2019-06-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Krishnan V. Ramani ,  Kai Troester ,  Frank C. Galloway ,  David N. Suggs ,  Michael D. Achenbach ,  Betty Ann McDaniel ,  Marius Evers

IPC: G06F9/28 ,  G06F9/30

Abstract: A system and method for tracking stores and loads to reduce load latency when forming the same memory address by bypassing a load store unit within an execution unit is disclosed. Store-load pairs which have a strong history of store-to-load forwarding are identified. Once identified, the load is memory renamed to the register stored by the store. The memory dependency predictor may also be used to detect loads that are dependent on a store but cannot be renamed. In such a configuration, the dependence is signaled to the load store unit and the load store unit uses the information to issue the load after the identified store has its physical address.

公开(公告)号：US10095637B2

公开(公告)日：2018-10-09

申请号：US15267094

申请日：2016-09-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Gregory W. Smaus ,  John M. King ,  Michael D. Achenbach ,  Kevin M. Lepak ,  Matthew A. Rafacz ,  Noah Bamford

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/14 ,  G06F9/52 ,  G06F9/30

Abstract: Techniques for improving execution of a lock instruction are provided herein. A lock instruction and younger instructions are allowed to speculatively retire prior to the store portion of the lock instruction committing its value to memory. These instructions thus do not have to wait for the lock instruction to complete before retiring. In the event that the processor detects a violation of the atomic or fencing properties of the lock instruction prior to committing the value of the lock instruction, the processor rolls back state and executes the lock instruction in a slow mode in which younger instructions are not allowed to retire until the stored value of the lock instruction is committed. Speculative retirement of these instructions results in increased processing speed, as instructions no longer need to wait to retire after execution of a lock instruction.

公开(公告)号：US20180074977A1

公开(公告)日：2018-03-15

申请号：US15267094

申请日：2016-09-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Gregory W. Smaus ,  John M. King ,  Michael D. Achenbach ,  Kevin M. Lepak ,  Matthew A. Rafacz ,  Noah Bamford

IPC: G06F12/14 ,  G06F9/52 ,  G06F9/30

CPC classification number: G06F12/1466 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3859 ,  G06F9/3863 ,  G06F9/528 ,  G06F2212/1052

Abstract: Techniques for improving execution of a lock instruction are provided herein. A lock instruction and younger instructions are allowed to speculatively retire prior to the store portion of the lock instruction committing its value to memory. These instructions thus do not have to wait for the lock instruction to complete before retiring. In the event that the processor detects a violation of the atomic or fencing properties of the lock instruction prior to committing the value of the lock instruction, the processor rolls back state and executes the lock instruction in a slow mode in which younger instructions are not allowed to retire until the stored value of the lock instruction is committed. Speculative retirement of these instructions results in increased processing speed, as instructions no longer need to wait to retire after execution of a lock instruction.

公开(公告)号：US11048506B2

公开(公告)日：2021-06-29

申请号：US16450897

申请日：2019-06-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Krishnan V. Ramani ,  Kai Troester ,  Frank C. Galloway ,  David N. Suggs ,  Michael D. Achenbach ,  Betty Ann McDaniel ,  Marius Evers

IPC: G06F9/28 ,  G06F9/30 ,  G06F9/38

Abstract: A system and method for tracking stores and loads to reduce load latency when forming the same memory address by bypassing a load store unit within an execution unit is disclosed. Store-load pairs which have a strong history of store-to-load forwarding are identified. Once identified, the load is memory renamed to the register stored by the store. The memory dependency predictor may also be used to detect loads that are dependent on a store but cannot be renamed. In such a configuration, the dependence is signaled to the load store unit and the load store unit uses the information to issue the load after the identified store has its physical address.

公开(公告)号：US20190196839A1

公开(公告)日：2019-06-27

申请号：US15853169

申请日：2017-12-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Christopher Spence Oliver ,  Hanbing Liu ,  Christopher James Burke ,  Michael D. Achenbach

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3855 ,  G06F9/3005

Abstract: A system and method for increasing address generation operations per cycle is described. In particular, a unified address generation scheduler queue (AGSQ) is a single queue structure which is accessed by first and second pickers in a picking cycle. Picking collisions are avoided by assigning a first set of entries to the first picker and a second set of entries to the second picker. The unified AGSQ uses a shifting, collapsing queue structure to shift other micro-operations into issued entries, which in turn collapses the queue and re-balances the unified AGSQ. A second level and delayed picker picks a third micro-operation that is ready for issue in the picking cycle. The third micro-operation is picked from the remaining entries across the first set of entries and the second set of entries. The third micro-operation issues in a next picking cycle.

公开(公告)号：US10331357B2

公开(公告)日：2019-06-25

申请号：US15380778

申请日：2016-12-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Betty Ann McDaniel ,  Michael D. Achenbach ,  David N. Suggs ,  Frank C. Galloway ,  Kai Troester ,  Krishnan V. Ramani

IPC: G06F3/06 ,  G06F12/0871 ,  G06F12/0897 ,  G06F9/30

Abstract: A system and method for tracking stores and loads to reduce load latency when forming the same memory address by bypassing a load store unit within an execution unit is disclosed. The system and method include storing data in one or more memory dependent architectural register numbers (MdArns), allocating the one or more MdArns to a MEMFILE, writing the allocated one or more MdArns to a map file, wherein the map file contains a MdArn map to enable subsequent access to an entry in the MEMFILE, upon receipt of a load request, checking a base, an index, a displacement and a match/hit via the map file to identify an entry in the MEMFILE and an associated store, and on a hit, providing the entry responsive to the load request from the one or more MdArns.

公开(公告)号：US20180052613A1

公开(公告)日：2018-02-22

申请号：US15380778

申请日：2016-12-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Betty Ann McDaniel ,  Michael D. Achenbach ,  David N. Suggs ,  Frank C. Galloway ,  Kai Troester ,  Krishnan V. Ramani

IPC: G06F3/06 ,  G06F12/0871 ,  G06F12/0897

CPC classification number: G06F3/0611 ,  G06F3/0631 ,  G06F3/0643 ,  G06F3/0659 ,  G06F3/0673 ,  G06F9/30 ,  G06F12/0871 ,  G06F12/0897 ,  G06F2212/1024 ,  G06F2212/304 ,  G06F2212/463 ,  G06F2212/604

Abstract: A system and method for tracking stores and loads to reduce load latency when forming the same memory address by bypassing a load store unit within an execution unit is disclosed. The system and method include storing data in one or more memory dependent architectural register numbers (MdArns), allocating the one or more MdArns to a MEMFILE, writing the allocated one or more MdArns to a map file, wherein the map file contains a MdArn map to enable subsequent access to an entry in the MEMFILE, upon receipt of a load request, checking a base, an index, a displacement and a match/hit via the map file to identify an entry in the MEMFILE and an associated store, and on a hit, providing the entry responsive to the load request from the one or more MdArns.