公开(公告)号：US20240311199A1

公开(公告)日：2024-09-19

申请号：US18120646

申请日：2023-03-13

Applicant: Advanced MICRO DEVICES, INC.

Inventor： Nicolai Haehnle ,  Mark Leather ,  Brian Emberling ,  Michael John Bedy ,  Daniel Schneider

IPC: G06F9/50 ,  G06F9/52

CPC classification number: G06F9/505 ,  G06F9/522

Abstract: A program code executing on a processing system includes one or more instructions each identifying a workload that includes a plurality of waves and each identifying resource allocations for the plurality of waves of the workgroup. In response to receiving an instruction identifying a workload and resource allocations for the plurality of waves of the workgroup, a processor allocates a first set of processing resources to a compute unit of the processor based on the resource allocations for the plurality of waves. The compute unit then performs operations for the workgroup using the allocated set of processing resources.

公开(公告)号：US10198789B2

公开(公告)日：2019-02-05

申请号：US15377998

申请日：2016-12-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Daniel Schneider ,  Fataneh Ghodrat

IPC: G06T1/60 ,  G06F12/0815 ,  G06F12/0877 ,  G06F15/80 ,  G06T15/00 ,  G06T1/20

Abstract: Techniques for allowing cache access returns out of order are disclosed. A return ordering queue exists for each of several cache access types and stores outstanding cache accesses in the order in which those accesses were made. When a cache access request for a particular type is at the head of the return ordering queue for that type and the cache access is available for return to the wavefront that made that access, the cache system returns the cache access to the wavefront. Thus, cache accesses can be returned out of order with respect to cache accesses of different types. Allowing out-of-order returns can help to improve latency, for example in the situation where a relatively low-latency access type (e.g., a read) is issued after a relatively high-latency access type (e.g., a texture sampler operation).

公开(公告)号：US20180165790A1

公开(公告)日：2018-06-14

申请号：US15377998

申请日：2016-12-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Daniel Schneider ,  Fataneh Ghodrat

IPC: G06T1/60 ,  G06F12/0877 ,  G06F12/0815 ,  G06F15/80

CPC classification number: G06T1/60 ,  G06F12/0815 ,  G06F12/0877 ,  G06F15/8007 ,  G06F2212/455 ,  G06F2212/60 ,  G06F2212/621 ,  G06T1/20 ,  G06T15/005

Abstract: Techniques for allowing cache access returns out of order are disclosed. A return ordering queue exists for each of several cache access types and stores outstanding cache accesses in the order in which those accesses were made. When a cache access request for a particular type is at the head of the return ordering queue for that type and the cache access is available for return to the wavefront that made that access, the cache system returns the cache access to the wavefront. Thus, cache accesses can be returned out of order with respect to cache accesses of different types. Allowing out-of-order returns can help to improve latency, for example in the situation where a relatively low-latency access type (e.g., a read) is issued after a relatively high-latency access type (e.g., a texture sampler operation).