公开(公告)号：US20190102175A1

公开(公告)日：2019-04-04

申请号：US15843965

申请日：2017-12-15

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts ,  Elliot H. Mednick ,  David John Cownie

IPC: G06F9/30 ,  G06F7/483

Abstract: A hybrid floating-point arithmetic processor includes a scheduler, a hybrid register file, and a hybrid arithmetic operation circuit. The scheduler has an input for receiving floating-point instructions, and an output for providing decoded register numbers in response to the floating-point instructions. The hybrid register file is coupled to the scheduler and contains circuitry for storing a plurality of floating-point numbers each represented by a digital sign bit, a digital exponent, and an analog mantissa. The hybrid register file has an output for providing selected ones of the plurality of floating-point numbers in response to the decoded register numbers. The hybrid arithmetic operation circuit is coupled to the scheduler and to the hybrid register file, for performing a hybrid arithmetic operation between two floating-point numbers selected by the scheduler and providing a hybrid result represented by a result digital sign bit, a result digital exponent, and a result analog mantissa.

公开(公告)号：US10289413B2

公开(公告)日：2019-05-14

申请号：US15843965

申请日：2017-12-15

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts ,  Elliot H. Mednick ,  David John Cownie

IPC: G06F9/30 ,  G06F7/483

Abstract: A hybrid floating-point arithmetic processor includes a scheduler, a hybrid register file, and a hybrid arithmetic operation circuit. The scheduler has an input for receiving floating-point instructions, and an output for providing decoded register numbers in response to the floating-point instructions. The hybrid register file is coupled to the scheduler and contains circuitry for storing a plurality of floating-point numbers each represented by a digital sign bit, a digital exponent, and an analog mantissa. The hybrid register file has an output for providing selected ones of the plurality of floating-point numbers in response to the decoded register numbers. The hybrid arithmetic operation circuit is coupled to the scheduler and to the hybrid register file, for performing a hybrid arithmetic operation between two floating-point numbers selected by the scheduler and providing a hybrid result represented by a result digital sign bit, a result digital exponent, and a result analog mantissa.