公开(公告)号：US11550728B2

公开(公告)日：2023-01-10

申请号：US16586183

申请日：2019-09-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Derrick Allen Aguren ,  Eric H. Van Tassell ,  Gabriel H. Loh ,  Jay Fleischman

IPC: G06F12/00 ,  G06F12/06 ,  G06F12/1009 ,  G06F12/14 ,  G06F9/455 ,  G06F12/0891 ,  G06F9/54

Abstract: A processing system includes a processor, a memory, and an operating system that are used to allocate a page table caching memory object (PTCM) for a user of the processing system. An allocation of the PTCM is requested from a PTCM allocation system. In order to allocate the PTCM, a plurality of physical memory pages from a memory are allocated to store a PTCM page table that is associated with the PTCM. A lockable region of a cache is designated to hold a copy of the PTCM page table, after which the lockable region of the cache is subsequently locked. The PTCM page table is populated with page table entries associated with the PTCM and copied to the locked region of the cache.

公开(公告)号：US11663001B2

公开(公告)日：2023-05-30

申请号：US16194981

申请日：2018-11-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Sanchari Sen ,  Derrick Allen Aguren ,  Joseph Lee Greathouse

IPC: G06F9/30 ,  G06F9/38 ,  G06F17/16 ,  G06N3/04

CPC classification number: G06F9/30014 ,  G06F9/30036 ,  G06F9/3887 ,  G06F17/16 ,  G06N3/04

Abstract: Systems, apparatuses, and methods for implementing a family of lossy sparse load single instruction, multiple data (SIMD) instructions are disclosed. A lossy sparse load unit (LSLU) loads a plurality of values from one or more input vector operands and determines how many non-zero values are included in one or more input vector operands of a given instruction. If the one or more input vector operands have less than a threshold number of non-zero values, then the LSLU causes an instruction for processing the one or more input vector operands to be skipped. In this case, the processing of the instruction of the one or more input vector operands is deemed to be redundant. If the one or more input vector operands have greater than or equal to the threshold number of non-zero values, then the LSLU causes an instruction for processing the input vector operand(s) to be executed.

公开(公告)号：US20200159529A1

公开(公告)日：2020-05-21

申请号：US16194981

申请日：2018-11-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Sanchari Sen ,  Derrick Allen Aguren ,  Joseph Lee Greathouse

IPC: G06F9/30 ,  G06F17/16 ,  G06F9/38 ,  G06N3/04

Abstract: Systems, apparatuses, and methods for implementing a family of lossy sparse load single instruction, multiple data (SIMD) instructions are disclosed. A lossy sparse load unit (LSLU) loads a plurality of values from one or more input vector operands and determines how many non-zero values are included in one or more input vector operands of a given instruction. If the one or more input vector operands have less than a threshold number of non-zero values, then the LSLU causes an instruction for processing the one or more input vector operands to be skipped. In this case, the processing of the instruction of the one or more input vector operands is deemed to be redundant. If the one or more input vector operands have greater than or equal to the threshold number of non-zero values, then the LSLU causes an instruction for processing the input vector operand(s) to be executed.

公开(公告)号：US11645207B2

公开(公告)日：2023-05-09

申请号：US17132769

申请日：2020-12-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Masab Ahmad ,  Derrick Allen Aguren

IPC: G06F12/10 ,  G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/6028

Abstract: A system and method for efficiently processing memory requests are described. A processing unit includes at least a processor core, a cache, and a non-cache storage buffer capable of storing data prevented from being stored in the cache. While processing a memory request targeting the non-cache storage buffer, the processor core inspects a flag stored in a tag of the memory request. The processor core prevents data prefetching into one or more of the non-cache storage buffer and the cache based on determining the flag specifies preventing data prefetching into one or more of the non-cache storage buffer and the cache using the target address of the memory request during processing of this instance of the memory request. While processing a prefetch hint instruction, the processor core determines from the tag whether to prevent prefetching.

公开(公告)号：US20220100664A1

公开(公告)日：2022-03-31

申请号：US17132769

申请日：2020-12-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Masab Ahmad ,  Derrick Allen Aguren

IPC: G06F12/0862

Abstract: A system and method for efficiently processing memory requests are described. A processing unit includes at least a processor core, a cache, and a non-cache storage buffer capable of storing data prevented from being stored in the cache. While processing a memory request targeting the non-cache storage buffer, the processor core inspects a flag stored in a tag of the memory request. The processor core prevents data prefetching into one or more of the non-cache storage buffer and the cache based on determining the flag specifies preventing data prefetching into one or more of the non-cache storage buffer and the cache using the target address of the memory request during processing of this instance of the memory request. While processing a prefetch hint instruction, the processor core determines from the tag whether to prevent prefetching.