公开(公告)号：US20230030679A1

公开(公告)日：2023-02-02

申请号：US17386115

申请日：2021-07-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Jagadish B. Kotra ,  John Kalamatianos ,  Gagandeep Panwar

IPC: G06F12/02 ,  G06F12/0817 ,  G06F12/06 ,  G06F9/30

Abstract: A technical solution to the technical problem of how to improve dispatch throughput for memory-centric commands bypasses address checking for certain memory-centric commands. Implementations include using an Address Check Bypass (ACB) bit to specify whether address checking should be performed for a memory-centric command. ACB bit values are specified in memory-centric instructions, automatically specified by a process, such as a compiler, or by host hardware, such as dispatch hardware, based upon whether a memory-centric command explicitly references memory. Implementations include bypassing, i.e., not performing, address checking for memory-centric commands that do not access memory and also for memory-centric commands that do access memory, but that have the same physical address as a prior memory-centric command that explicitly accessed memory to ensure that any data in caches was flushed to memory and/or invalidated.

公开(公告)号：US12019547B2

公开(公告)日：2024-06-25

申请号：US17386115

申请日：2021-07-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Jagadish B. Kotra ,  John Kalamatianos ,  Gagandeep Panwar

IPC: G06F12/08 ,  G06F9/30 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0815 ,  G06F12/0817

CPC classification number: G06F12/0815 ,  G06F9/30047 ,  G06F12/0238 ,  G06F12/0653 ,  G06F12/0817

Abstract: A technical solution to the technical problem of how to improve dispatch throughput for memory-centric commands bypasses address checking for certain memory-centric commands. Implementations include using an Address Check Bypass (ACB) bit to specify whether address checking should be performed for a memory-centric command. ACB bit values are specified in memory-centric instructions, automatically specified by a process, such as a compiler, or by host hardware, such as dispatch hardware, based upon whether a memory-centric command explicitly references memory. Implementations include bypassing, i.e., not performing, address checking for memory-centric commands that do not access memory and also for memory-centric commands that do access memory, but that have the same physical address as a prior memory-centric command that explicitly accessed memory to ensure that any data in caches was flushed to memory and/or invalidated.