公开(公告)号：US11687615B2

公开(公告)日：2023-06-27

申请号：US16232768

申请日：2018-12-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Hua Zhang

IPC: G06F17/16 ,  G06N20/00

CPC classification number: G06F17/16 ,  G06N20/00

Abstract: Systems, apparatuses, and methods for implementing a tiling algorithm for a matrix math instruction set are disclosed. A system includes at least a memory, a cache, a processor, and a plurality of compute units. The memory stores a plurality of matrix elements in a linear format, and the processor converts the plurality of matrix elements from the linear format to a tiling format. Each compute unit retrieves a plurality of matrix elements from the memory into the cache. Each compute unit includes a matrix operations unit which loads the plurality of matrix elements of corresponding tile(s) from the cache and performs a matrix operation on the plurality of matrix elements to generate a result in the tiling format. The system generates a classification of a first dataset based on results of the matrix operations.

公开(公告)号：US20230186084A1

公开(公告)日：2023-06-15

申请号：US18050939

申请日：2022-10-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Song Zhang ,  Jiantan Liu ,  Hua Zhang ,  Min Yu

IPC: G06N3/08 ,  G06N3/04 ,  G06F18/21 ,  G06V10/82 ,  G06V10/44 ,  G06V10/50 ,  G06V10/94

CPC classification number: G06N3/08 ,  G06N3/04 ,  G06F18/217 ,  G06V10/82 ,  G06V10/454 ,  G06V10/449 ,  G06V10/50 ,  G06V10/955

Abstract: Systems, apparatuses, and methods for converting data to a tiling format when implementing convolutional neural networks are disclosed. A system includes at least a memory, a cache, a processor, and a plurality of compute units. The memory stores a first buffer and a second buffer in a linear format, where the first buffer stores convolutional filter data and the second buffer stores image data. The processor converts the first and second buffers from the linear format to third and fourth buffers, respectively, in a tiling format. The plurality of compute units load the tiling-formatted data from the third and fourth buffers in memory to the cache and then perform a convolutional filter operation on the tiling-formatted data. The system generates a classification of a first dataset based on a result of the convolutional filter operation.

公开(公告)号：US11494592B2

公开(公告)日：2022-11-08

申请号：US17006533

申请日：2020-08-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Song Zhang ,  Jiantan Liu ,  Hua Zhang ,  Min Yu

IPC: G06N3/08 ,  G06K9/62 ,  G06N3/04

Abstract: Systems, apparatuses, and methods for converting data to a tiling format when implementing convolutional neural networks are disclosed. A system includes at least a memory, a cache, a processor, and a plurality of compute units. The memory stores a first buffer and a second buffer in a linear format, where the first buffer stores convolutional filter data and the second buffer stores image data. The processor converts the first and second buffers from the linear format to third and fourth buffers, respectively, in a tiling format. The plurality of compute units load the tiling-formatted data from the third and fourth buffers in memory to the cache and then perform a convolutional filter operation on the tiling-formatted data. The system generates a classification of a first dataset based on a result of the convolutional filter operation.

公开(公告)号：US10762392B2

公开(公告)日：2020-09-01

申请号：US16234956

申请日：2018-12-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Song Zhang ,  Jiantan Liu ,  Hua Zhang ,  Min Yu

IPC: G06K9/62 ,  G06N3/08 ,  G06N3/04

Abstract: Systems, apparatuses, and methods for converting data to a tiling format when implementing convolutional neural networks are disclosed. A system includes at least a memory, a cache, a processor, and a plurality of compute units. The memory stores a first buffer and a second buffer in a linear format, where the first buffer stores convolutional filter data and the second buffer stores image data. The processor converts the first and second buffers from the linear format to third and fourth buffers, respectively, in a tiling format. The plurality of compute units load the tiling-formatted data from the third and fourth buffers in memory to the cache and then perform a convolutional filter operation on the tiling-formatted data. The system generates a classification of a first dataset based on a result of the convolutional filter operation.

公开(公告)号：US11900253B2

公开(公告)日：2024-02-13

申请号：US18050939

申请日：2022-10-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Song Zhang ,  Jiantan Liu ,  Hua Zhang ,  Min Yu

IPC: G06N3/08 ,  G06N3/04 ,  G06F18/21 ,  G06V10/82 ,  G06V10/44 ,  G06V10/50 ,  G06V10/94

CPC classification number: G06N3/08 ,  G06F18/217 ,  G06N3/04 ,  G06V10/449 ,  G06V10/454 ,  G06V10/50 ,  G06V10/82 ,  G06V10/955

Abstract: Systems, apparatuses, and methods for converting data to a tiling format when implementing convolutional neural networks are disclosed. A system includes at least a memory, a cache, a processor, and a plurality of compute units. The memory stores a first buffer and a second buffer in a linear format, where the first buffer stores convolutional filter data and the second buffer stores image data. The processor converts the first and second buffers from the linear format to third and fourth buffers, respectively, in a tiling format. The plurality of compute units load the tiling-formatted data from the third and fourth buffers in memory to the cache and then perform a convolutional filter operation on the tiling-formatted data. The system generates a classification of a first dataset based on a result of the convolutional filter operation.