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公开(公告)号：US11900253B2
公开(公告)日：2024-02-13
申请号：US18050939
申请日：2022-10-28
Applicant: Advanced Micro Devices, Inc.
Inventor： Song Zhang , Jiantan Liu , Hua Zhang , Min Yu
CPC classification number: G06N3/08 , G06F18/217 , G06N3/04 , G06V10/449 , G06V10/454 , G06V10/50 , G06V10/82 , G06V10/955
Abstract: Systems, apparatuses, and methods for converting data to a tiling format when implementing convolutional neural networks are disclosed. A system includes at least a memory, a cache, a processor, and a plurality of compute units. The memory stores a first buffer and a second buffer in a linear format, where the first buffer stores convolutional filter data and the second buffer stores image data. The processor converts the first and second buffers from the linear format to third and fourth buffers, respectively, in a tiling format. The plurality of compute units load the tiling-formatted data from the third and fourth buffers in memory to the cache and then perform a convolutional filter operation on the tiling-formatted data. The system generates a classification of a first dataset based on a result of the convolutional filter operation.
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公开(公告)号：US11095910B2
公开(公告)日：2021-08-17
申请号：US16706297
申请日：2019-12-06
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
IPC: H04N19/187 , H04N19/33 , H04N19/59 , H04N19/423 , H04N19/159 , H04N19/117 , H04N19/80
Abstract: A system and method for scalable video coding that includes base layer having lower resolution encoding, enhanced layer having higher resolution encoding and the data transferring between two layers. The system and method provides several methods to reduce bandwidth of inter-layer transfers while at the same time reducing memory requirements. Due to less memory access, the system clock frequency can be lowered so that system power consumption is lowered as well. The system avoids having prediction data from base layer to enhanced layer to be up-sampled for matching resolution in the enhanced layer as transferring up-sampled data can impose a big burden on memory bandwidth.
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公开(公告)号：US11863769B2
公开(公告)日：2024-01-02
申请号：US17403191
申请日：2021-08-16
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
IPC: H04N19/159 , H04N19/117 , H04N19/187 , H04N19/33 , H04N19/423 , H04N19/80 , H04N19/59
CPC classification number: H04N19/423 , H04N19/117 , H04N19/159 , H04N19/187 , H04N19/33 , H04N19/59 , H04N19/80
Abstract: A system configured to perform scalable video encoding is provided. The system includes a memory; and a processing unit, wherein the processing unit is configured to: receive inter-layer data and a current picture, wherein the current picture has a base layer; upsample the inter-layer data to generate residual data and reconstruction data, wherein the inter-layer data includes a base mode flag; and encode the current picture to an enhanced layer using the upsampled inter-layer data based on a block type of the base layer and the base mode flag.
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公开(公告)号：US20210377552A1
公开(公告)日：2021-12-02
申请号：US17403191
申请日：2021-08-16
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
IPC: H04N19/423 , H04N19/159 , H04N19/117 , H04N19/187 , H04N19/33
Abstract: A system configured to perform scalable video encoding is provided. The system includes a memory; and a processing unit, wherein the processing unit is configured to: receive inter-layer data and a current picture, wherein the current picture has a base layer; upsample the inter-layer data to generate residual data and reconstruction data, wherein the inter-layer data includes a base mode flag; and encode the current picture to an enhanced layer using the upsampled inter-layer data based on a block type of the base layer and the base mode flag.
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公开(公告)号：US10762392B2
公开(公告)日：2020-09-01
申请号：US16234956
申请日：2018-12-28
Applicant: Advanced Micro Devices, Inc.
Inventor： Song Zhang , Jiantan Liu , Hua Zhang , Min Yu
Abstract: Systems, apparatuses, and methods for converting data to a tiling format when implementing convolutional neural networks are disclosed. A system includes at least a memory, a cache, a processor, and a plurality of compute units. The memory stores a first buffer and a second buffer in a linear format, where the first buffer stores convolutional filter data and the second buffer stores image data. The processor converts the first and second buffers from the linear format to third and fourth buffers, respectively, in a tiling format. The plurality of compute units load the tiling-formatted data from the third and fourth buffers in memory to the cache and then perform a convolutional filter operation on the tiling-formatted data. The system generates a classification of a first dataset based on a result of the convolutional filter operation.
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Patent Agency Ranking
公开(公告)号：US10659796B2
公开(公告)日：2020-05-19
申请号：US16126704
申请日：2018-09-10
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
IPC: H04N19/159 , H04N19/33 , H04N19/423 , H04N19/117 , H04N19/187 , H04N19/80 , H04N19/59
Abstract: A system and method for scalable video coding that includes base layer having lower resolution encoding, enhanced layer having higher resolution encoding and the data transferring between two layers. The system and method provides several methods to reduce bandwidth of inter-layer transfers while at the same time reducing memory requirements. Due to less memory access, the system clock frequency can be lowered so that system power consumption is lowered as well. The system avoids having prediction data from base layer to enhanced layer to be up-sampled for matching resolution in the enhanced layer as transferring up-sampled data can impose a big burden on memory bandwidth.
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公开(公告)号：US20190028725A1
公开(公告)日：2019-01-24
申请号：US16126704
申请日：2018-09-10
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
IPC: H04N19/423 , H04N19/33 , H04N19/159 , H04N19/117 , H04N19/187 , H04N19/59 , H04N19/80
Abstract: A system and method for scalable video coding that includes base layer having lower resolution encoding, enhanced layer having higher resolution encoding and the data transferring between two layers. The system and method provides several methods to reduce bandwidth of inter-layer transfers while at the same time reducing memory requirements. Due to less memory access, the system clock frequency can be lowered so that system power consumption is lowered as well. The system avoids having prediction data from base layer to enhanced layer to be up-sampled for matching resolution in the enhanced layer as transferring up-sampled data can impose a big burden on memory bandwidth.
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公开(公告)号：US20230186084A1
公开(公告)日：2023-06-15
申请号：US18050939
申请日：2022-10-28
Applicant: Advanced Micro Devices, Inc.
Inventor： Song Zhang , Jiantan Liu , Hua Zhang , Min Yu
CPC classification number: G06N3/08 , G06N3/04 , G06F18/217 , G06V10/82 , G06V10/454 , G06V10/449 , G06V10/50 , G06V10/955
Abstract: Systems, apparatuses, and methods for converting data to a tiling format when implementing convolutional neural networks are disclosed. A system includes at least a memory, a cache, a processor, and a plurality of compute units. The memory stores a first buffer and a second buffer in a linear format, where the first buffer stores convolutional filter data and the second buffer stores image data. The processor converts the first and second buffers from the linear format to third and fourth buffers, respectively, in a tiling format. The plurality of compute units load the tiling-formatted data from the third and fourth buffers in memory to the cache and then perform a convolutional filter operation on the tiling-formatted data. The system generates a classification of a first dataset based on a result of the convolutional filter operation.
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公开(公告)号：US11494592B2
公开(公告)日：2022-11-08
申请号：US17006533
申请日：2020-08-28
Applicant: Advanced Micro Devices, Inc.
Inventor： Song Zhang , Jiantan Liu , Hua Zhang , Min Yu
Abstract: Systems, apparatuses, and methods for converting data to a tiling format when implementing convolutional neural networks are disclosed. A system includes at least a memory, a cache, a processor, and a plurality of compute units. The memory stores a first buffer and a second buffer in a linear format, where the first buffer stores convolutional filter data and the second buffer stores image data. The processor converts the first and second buffers from the linear format to third and fourth buffers, respectively, in a tiling format. The plurality of compute units load the tiling-formatted data from the third and fourth buffers in memory to the cache and then perform a convolutional filter operation on the tiling-formatted data. The system generates a classification of a first dataset based on a result of the convolutional filter operation.
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公开(公告)号：US10085017B2
公开(公告)日：2018-09-25
申请号：US13689212
申请日：2012-11-29
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
IPC: H04N19/117 , H04N19/59 , H04N19/159 , H04N19/187 , H04N19/33 , H04N19/423 , H04N19/80
CPC classification number: H04N19/423 , H04N19/117 , H04N19/159 , H04N19/187 , H04N19/33 , H04N19/59 , H04N19/80
Abstract: A system and method for scalable video coding that includes base layer having lower resolution encoding, enhanced layer having higher resolution encoding and the data transferring between two layers. The system and method provides several methods to reduce bandwidth of inter-layer transfers while at the same time reducing memory requirements. Due to less memory access, the system clock frequency can be lowered so that system power consumption is lowered as well. The system avoids having prediction data from base layer to enhanced layer to be up-sampled for matching resolution in the enhanced layer as transferring up-sampled data can impose a big burden on memory bandwidth.
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