公开(公告)号：US12197735B2

公开(公告)日：2025-01-14

申请号：US18129390

申请日：2023-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Vignesh Adhinarayanan ,  Michael Ignatowski ,  Hyung-Dong Lee

IPC: G06F12/00 ,  G06F3/06

Abstract: A memory sprint controller, responsive to an indicator of an irregular memory access phase, causes a memory controller to enter a sprint mode in which it temporarily adjusts at least one timing parameter of a dynamic random access memory (DRAM) to reduce a time in which a designated number of activate (ACT) commands are allowed to be dispatched to the DRAM.

公开(公告)号：US20240329846A1

公开(公告)日：2024-10-03

申请号：US18129390

申请日：2023-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Vignesh Adhinarayanan ,  Michael Ignatowski ,  Hyung-Dong Lee

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0634 ,  G06F3/0673

Abstract: A memory sprint controller, responsive to an indicator of an irregular memory access phase, causes a memory controller to enter a sprint mode in which it temporarily adjusts at least one timing parameter of a dynamic random access memory (DRAM) to reduce a time in which a designated number of activate (ACT) commands are allowed to be dispatched to the DRAM.

公开(公告)号：US12086418B1

公开(公告)日：2024-09-10

申请号：US18129436

申请日：2023-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Vignesh Adhinarayanan ,  Michael Ignatowski ,  Hyung-Dong Lee

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0634 ,  G06F3/0673

Abstract: A memory sprint controller, responsive to an indicator of an irregular memory access phase, causes a memory controller to enter a sprint mode in which it temporarily adjusts at least one timing parameter of a dynamic random access memory (DRAM) to reduce a time in which a designated number of activate (ACT) commands are allowed to be dispatched to the DRAM.

公开(公告)号：US20240329847A1

公开(公告)日：2024-10-03

申请号：US18129436

申请日：2023-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Vignesh Adhinarayanan ,  Michael Ignatowski ,  Hyung-Dong Lee

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0673

Abstract: A memory sprint controller, responsive to an indicator of an irregular memory access phase, causes a memory controller to enter a sprint mode in which it temporarily adjusts at least one timing parameter of a dynamic random access memory (DRAM) to reduce a time in which a designated number of activate (ACT) commands are allowed to be dispatched to the DRAM.