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公开(公告)号：US20200344039A1
公开(公告)日：2020-10-29
申请号：US16709472
申请日：2019-12-10
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Varun Gupta , Milam Paraschou , Gerald R. Talbot , Gurunath Dollin , Damon Tohidi , Eric Ian Carpenter , Chad S. Gallun , Jeffrey Cooper , Hanwoo Cho , Thomas H. Likens, III , Scott F. Dow , Michael J. Tresidder
Abstract: Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.
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公开(公告)号：US12287753B2
公开(公告)日：2025-04-29
申请号：US18216908
申请日：2023-06-30
Applicant: ATI Technologies ULC , Advanced Micro Devices, Inc.
Inventor： Gordon Caruk , Maurice B. Steinman , Gerald R. Talbot , Joseph D. Macri
Abstract: A link controller includes a Peripheral Component Interconnect Express (PCIe) physical layer circuit for coupling to a communication link and providing a data path over the communication link, a first data link layer controller which operates according to a PCIe protocol, and a second data link layer controller which operates according to a non-PCIe protocol. A multiplexer-demultiplexer selectively connects both data link layer controllers to the PCIe physical layer circuit. A protocol translation circuit is coupled between the multiplexer-demultiplexer and the second data link layer controller, the protocol translation circuit receiving traffic data from the second data link layer controller in a non-PCIe format, encapsulating the non-PCIe format in a PCIe format, and passing traffic data to the multiplexer-demultiplexer circuit.
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公开(公告)号：US10698856B1
公开(公告)日：2020-06-30
申请号：US16223873
申请日：2018-12-18
Applicant: ATI Technologies ULC , Advanced Micro Devices, Inc.
Inventor： Gordon Caruk , Gerald R. Talbot
Abstract: A link controller, method, and data processing platform are provided with dual-protocol capability. The link controller includes a physical layer circuit for providing a data lane over a communication link, a first data link layer controller which operates according to a first protocol, and a second data link layer controller which operates according to a second protocol. A multiplexer/demultiplexer selectively connects both data link layer controllers to the physical layer circuit. A link training and status state machine (LTSSM) selectively controls the physical layer circuit to transmit and receive first training ordered sets over the data lane, and inside the training ordered sets, transmit and receive alternative protocol negotiation information over the data lane. In response to receiving the alternative protocol negotiation information, the LTSSM causes the multiplexer/demultiplexer to selectively connect the physical layer circuit to the second data link layer controller.
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公开(公告)号：US20170373944A1
公开(公告)日：2017-12-28
申请号：US15192287
申请日：2016-06-24
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Stanley Ames Lackey, JR. , Damon Tohidi , Gerald R. Talbot , Edoardo Prete
Abstract: Systems, apparatuses, and methods for utilizing training sequences on a replica lane are described. A transmitter is coupled to a receiver via a communication channel with a plurality of lanes. One of the lanes is a replica lane used for tracking the drift in the optimal sampling point due to temperature variations, power supply variations, or other factors. While data is sent on the data lanes, test patterns are sent on the replica lane to determine if the optimal sampling point for the replica lane has drifted since a previous test. If the optimal sampling point has drifted for the replica lane, adjustments are made to the sampling point of the replica lane and to the sampling points of the data lanes.
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公开(公告)号：US20170373788A1
公开(公告)日：2017-12-28
申请号：US15191322
申请日：2016-06-23
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Stanley Ames Lackey, JR. , Damon Tohidi , Gerald R. Talbot , Edoardo Prete
CPC classification number: H04L1/0002 , H04L1/0073 , H04L1/244 , H04L7/0037 , H04L7/043 , H04L7/10 , H04L25/14 , H04L2012/5681
Abstract: Systems, apparatuses, and methods for implementing asynchronous feedback training sequences are described. A transmitter transmits a training sequence indication to a receiver via a communication channel including a plurality of data lines. The training sequence indication includes a bit sequence to indicate the beginning of a training sequence. The indication includes a transition from a zero to a one at the midpoint of a supercycle of ‘N’ clock cycles in length, followed by a predetermined number of ones. The training sequence indication is then followed by a test pattern. The beginning of the test pattern occurs at the end of a supercycle. The receiver determines if there are any errors in the received test pattern, and then sends feedback to the transmitter that indicates whether any errors were detected. Responsive to receiving the feedback, the transmitter alters delay settings for one or more of the data lines.
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Patent Agency Ranking
公开(公告)号：US11283589B2
公开(公告)日：2022-03-22
申请号：US17128720
申请日：2020-12-21
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Varun Gupta , Milam Paraschou , Gerald R. Talbot , Gurunath Dollin , Damon Tohidi , Eric Ian Carpenter , Chad S. Gallun , Jeffrey Cooper , Hanwoo Cho , Thomas H. Likens, III , Scott F. Dow , Michael J. Tresidder
Abstract: Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.
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公开(公告)号：US20210028995A1
公开(公告)日：2021-01-28
申请号：US16993678
申请日：2020-08-14
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Stanley Ames Lackey, JR. , Damon Tohidi , Gerald R. Talbot , Edoardo Prete
Abstract: Systems, apparatuses, and methods for utilizing training sequences on a replica lane are described. A transmitter is coupled to a receiver via a communication channel with a plurality of lanes. One of the lanes is a replica lane used for tracking the drift in the optimal sampling point due to temperature variations, power supply variations, or other factors. While data is sent on the data lanes, test patterns are sent on the replica lane to determine if the optimal sampling point for the replica lane has drifted since a previous test. If the optimal sampling point has drifted for the replica lane, adjustments are made to the sampling point of the replica lane and to the sampling points of the data lanes.
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公开(公告)号：US10749756B2
公开(公告)日：2020-08-18
申请号：US15192287
申请日：2016-06-24
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Stanley Ames Lackey, Jr. , Damon Tohidi , Gerald R. Talbot , Edoardo Prete
Abstract: Systems, apparatuses, and methods for utilizing training sequences on a replica lane are described. A transmitter is coupled to a receiver via a communication channel with a plurality of lanes. One of the lanes is a replica lane used for tracking the drift in the optimal sampling point due to temperature variations, power supply variations, or other factors. While data is sent on the data lanes, test patterns are sent on the replica lane to determine if the optimal sampling point for the replica lane has drifted since a previous test. If the optimal sampling point has drifted for the replica lane, adjustments are made to the sampling point of the replica lane and to the sampling points of the data lanes.
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公开(公告)号：US10103837B2
公开(公告)日：2018-10-16
申请号：US15191322
申请日：2016-06-23
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Stanley Ames Lackey, Jr. , Damon Tohidi , Gerald R. Talbot , Edoardo Prete
Abstract: Systems, apparatuses, and methods for implementing asynchronous feedback training sequences are described. A transmitter transmits a training sequence indication to a receiver via a communication channel including a plurality of data lines. The training sequence indication includes a bit sequence to indicate the beginning of a training sequence. The indication includes a transition from a zero to a one at the midpoint of a supercycle of ‘N’ clock cycles in length, followed by a predetermined number of ones. The training sequence indication is then followed by a test pattern. The beginning of the test pattern occurs at the end of a supercycle. The receiver determines if there are any errors in the received test pattern, and then sends feedback to the transmitter that indicates whether any errors were detected. Responsive to receiving the feedback, the transmitter alters delay settings for one or more of the data lines.
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公开(公告)号：US11805026B2
公开(公告)日：2023-10-31
申请号：US16993678
申请日：2020-08-14
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Stanley Ames Lackey, Jr. , Damon Tohidi , Gerald R. Talbot , Edoardo Prete
IPC: H04L41/147 , H04L43/50 , H04L43/0852 , H04L7/10 , H04L43/0823 , H04L25/14 , H04L7/06 , H04L7/00 , H04L7/04
CPC classification number: H04L41/147 , H04L7/06 , H04L7/10 , H04L25/14 , H04L43/0823 , H04L43/0852 , H04L43/50 , H04L7/0041 , H04L7/043
Abstract: Systems, apparatuses, and methods for utilizing training sequences on a replica lane are described. A transmitter is coupled to a receiver via a communication channel with a plurality of lanes. One of the lanes is a replica lane used for tracking the drift in the optimal sampling point due to temperature variations, power supply variations, or other factors. While data is sent on the data lanes, test patterns are sent on the replica lane to determine if the optimal sampling point for the replica lane has drifted since a previous test. If the optimal sampling point has drifted for the replica lane, adjustments are made to the sampling point of the replica lane and to the sampling points of the data lanes.
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