公开(公告)号：US20250088193A1

公开(公告)日：2025-03-13

申请号：US18466221

申请日：2023-09-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Srikanth Reddy Gruddanti ,  Debasish Dwibedy ,  Manoj N. Kulkarni ,  Prasant Kumar Vallur ,  Priyadarshi Saxena

IPC: H03L7/081 ,  G06F1/04 ,  H03K3/011

Abstract: A method for driver calibration in die-to-die interfaces can include calibrating a delay lock loop of a delay line unit cell, by at least one processor, based on drive and load conditions of one or more driver unit cells of a physical layer of a die-to-die interconnect. The method can additionally include generating a clock signal, by the at least one processor, based on the delay lock loop. The method can further include communicating data, by the at least one processor, over the die-to-die interconnect based on the clock signal. Various other methods and systems are also disclosed.

公开(公告)号：US20240395295A1

公开(公告)日：2024-11-28

申请号：US18201611

申请日：2023-05-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Srikanth Reddy Gruddanti ,  Prasant Kumar Vallur ,  David Da-Wei Lin ,  Manoj N. Kulkarni ,  Priyadarshi Saxena

IPC: G11C7/22 ,  G11C7/10 ,  H03K19/003

Abstract: A signal processing circuit includes an analog front-end circuit and a digital delay circuit. The analog circuit receives a clock signal and provides a compensated clock signal. The digital delay circuit is coupled to the analog front-end circuit and provides a compensated sample clock signal in response to delaying the compensated clock signal. The analog circuit measures a variation of a power supply voltage and adjusts a gain through the analog circuit according to a measured variation of the power supply voltage.