公开(公告)号：US11960435B2

公开(公告)日：2024-04-16

申请号：US17692147

申请日：2022-03-10

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Pradeep Jayaraman ,  Dean Gonzales ,  Gerald R. Talbot ,  Ramon A. Mangaser ,  Michael J. Tresidder ,  Prasant Kumar Vallur ,  Srikanth Reddy Gruddanti ,  Krishna Reddy Mudimela Venkata ,  David H. McIntyre

IPC: G06F13/42 ,  H01L25/065

CPC classification number: G06F13/4291 ,  G06F13/4286 ,  H01L25/0652

Abstract: A semiconductor package for skew matching in a die-to-die interface, including: a first die; a second die aligned with the first die such that each connection point of a first plurality of connection points of the first die is substantially equidistant to a corresponding connection point of a second plurality of connection points of the second die; and a plurality of connection paths of a substantially same length, wherein each connection path of the plurality of connection paths couples a respective connection point of the first plurality of connection points to the corresponding connection point of the second plurality of connection points.

公开(公告)号：US10715139B2

公开(公告)日：2020-07-14

申请号：US16120836

申请日：2018-09-04

Applicant: Advanced Micro Devices, Inc.

Inventor： Rajesh Mangalore Anand ,  Jagadeesh Anathahalli Singrigowda ,  Girish Anathahalli Singrigowda ,  Prasant Kumar Vallur

IPC: H03K19/003 ,  H03K17/687

Abstract: Driver and pre-driver circuitry operate in an integrated circuit with two supply voltages. In one form, a reference voltage generation circuit is operable to respond to varying voltage supply conditions in which a driver may be subject to over voltage effects by generating a reference voltage based the first supply voltage when the second supply voltage is not available, and based on the second supply voltage when the first supply voltage is not available. A first drive signal generation circuit drives a pull-up transistor gate based on a data signal, varying the gate voltage between the second supply voltage and the reference voltage. A second drive signal generation circuit drives a pull-down transistor gate with a signal varying between the second supply voltage minus the reference voltage, and zero volts. In one form, certain gate-source voltages in the driver are maintained to be equal.

公开(公告)号：US12015412B1

公开(公告)日：2024-06-18

申请号：US18060857

申请日：2022-12-01

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Srikanth Reddy Gruddanti ,  Pradeep Jayaraman ,  Ramon A. Mangaser ,  Prasant Kumar Vallur ,  Krishna Reddy Mudimela Venkata ,  David H. McIntyre

IPC: H03K5/24 ,  H03K5/14 ,  H03L7/099 ,  H03K5/00

CPC classification number: H03K5/249 ,  H03K5/14 ,  H03L7/0998 ,  H03K2005/00286

Abstract: A semiconductor package includes a first die having a phase locked loop outputting a local clock signal and a strobe signal to a first transmit block of the first die. The strobe signal has a phase offset relative to the local clock signal. A second die is aligned with the first die so each of a first plurality of connection points of the first die is substantially equidistant to a corresponding connection point of a second plurality of connection points of the second die. A plurality of connection paths of a substantially same length couple a connection points of the first plurality of connection points to corresponding connection points of the second plurality of connection points. Different connection paths transmit data signals from the first die to the second die based on the local clock signal and transmit the strobe signal from the first die to the second die.

公开(公告)号：US11764789B2

公开(公告)日：2023-09-19

申请号：US17487569

申请日：2021-09-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Rajesh Mangalore Anand ,  Prasant Kumar Vallur ,  Piyush Gupta ,  Girish Anathahalli Singrigowda ,  Jagadeesh Anathahalli Singrigowda

IPC: H03K19/17788 ,  H03K19/0185 ,  H03K19/003

CPC classification number: H03K19/17788 ,  H03K19/00315 ,  H03K19/00384 ,  H03K19/018507

Abstract: Systems and techniques for applying voltage biases to gates of driver circuitry of an integrated circuit (IC) based on a detected bus voltage, IC supply voltage, or both are used to mitigate Electrical Over-Stress (EOS) issues in components of the driver circuitry caused, for instance, by high bus voltages in serial communication systems relative to maximum operating voltages of those components. A driver bias generator selectively applies bias voltages at gates of transistors of a stacked driver structure of an IC to prevent the voltage drop across any given transistor of the stacked driver structure from exceeding a predetermined threshold associated with the maximum operating voltage range of the transistors.

公开(公告)号：US20250088193A1

公开(公告)日：2025-03-13

申请号：US18466221

申请日：2023-09-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Srikanth Reddy Gruddanti ,  Debasish Dwibedy ,  Manoj N. Kulkarni ,  Prasant Kumar Vallur ,  Priyadarshi Saxena

IPC: H03L7/081 ,  G06F1/04 ,  H03K3/011

Abstract: A method for driver calibration in die-to-die interfaces can include calibrating a delay lock loop of a delay line unit cell, by at least one processor, based on drive and load conditions of one or more driver unit cells of a physical layer of a die-to-die interconnect. The method can additionally include generating a clock signal, by the at least one processor, based on the delay lock loop. The method can further include communicating data, by the at least one processor, over the die-to-die interconnect based on the clock signal. Various other methods and systems are also disclosed.

公开(公告)号：US20210409020A1

公开(公告)日：2021-12-30

申请号：US17081540

申请日：2020-10-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Jagadeesh Anathahalli Singrigowda ,  Ashish Sahu ,  Rajesh Mangalore Anand ,  Aniket Bharat Waghide ,  Girish Anathahalli Singrigowda ,  Prasant Kumar Vallur

IPC: H03K17/687 ,  H03K19/0948 ,  H03K19/0185 ,  H03K19/003 ,  H03K17/0812 ,  G01R19/165 ,  G05F3/20

Abstract: A driver circuit drives a high voltage I/O interface using stacked low voltage devices in the pull-up and pull-down portions of the driver. The transistor closest to the PAD in the pull-up portion receives a dynamically adjusted gate bias voltage adjusted based on the value of the data supplied to the output circuit and the transistor in the pull-down portion closest to the PAD receives the same dynamically adjusted gate bias voltage. The transistors closest to the power supply nodes receive gate voltages that are level shifted from the core voltage levels of the data supplied to the output circuit. The transistors in the middle of the pull-up and pull-down transistor stacks receive respective static gate voltages. The bias voltages are selected such that the gate-drain, source-drain, and gate-source voltages of the transistors in the output circuit do not exceed the voltage tolerance levels of the low voltage devices.

公开(公告)号：US20200076429A1

公开(公告)日：2020-03-05

申请号：US16120836

申请日：2018-09-04

Applicant: Advanced Micro Devices, Inc.

Inventor： Rajesh Mangalore Anand ,  Jagadeesh Anathahalli Singrigowda ,  Girish Anathahalli Singrigowda ,  Prasant Kumar Vallur

IPC: H03K17/687 ,  H03K19/003

Abstract: Driver and pre-driver circuitry operate in an integrated circuit with two supply voltages. In one form, a reference voltage generation circuit is operable to respond to varying voltage supply conditions in which a driver may be subject to over voltage effects by generating a reference voltage based the first supply voltage when the second supply voltage is not available, and based on the second supply voltage when the first supply voltage is not available. A first drive signal generation circuit drives a pull-up transistor gate based on a data signal, varying the gate voltage between the second supply voltage and the reference voltage. A second drive signal generation circuit drives a pull-down transistor gate with a signal varying between the second supply voltage minus the reference voltage, and zero volts. In one form, certain gate-source voltages in the driver are maintained to be equal.

公开(公告)号：US20240395295A1

公开(公告)日：2024-11-28

申请号：US18201611

申请日：2023-05-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Srikanth Reddy Gruddanti ,  Prasant Kumar Vallur ,  David Da-Wei Lin ,  Manoj N. Kulkarni ,  Priyadarshi Saxena

IPC: G11C7/22 ,  G11C7/10 ,  H03K19/003

Abstract: A signal processing circuit includes an analog front-end circuit and a digital delay circuit. The analog circuit receives a clock signal and provides a compensated clock signal. The digital delay circuit is coupled to the analog front-end circuit and provides a compensated sample clock signal in response to delaying the compensated clock signal. The analog circuit measures a variation of a power supply voltage and adjusts a gain through the analog circuit according to a measured variation of the power supply voltage.

公开(公告)号：US20230095805A1

公开(公告)日：2023-03-30

申请号：US17487569

申请日：2021-09-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Rajesh Mangalore Anand ,  Prasant Kumar Vallur ,  Piyush Gupta ,  Girish Anathahalli Singrigowda ,  Jagadeesh Anathahalli Singrigowda

IPC: H03K19/17788 ,  H03K19/003 ,  H03K19/0185

Abstract: Systems and techniques for applying voltage biases to gates of driver circuitry of an integrated circuit (IC) based on a detected bus voltage, IC supply voltage, or both are used to mitigate Electrical Over-Stress (EOS) issues in components of the driver circuitry caused, for instance, by high bus voltages in serial communication systems relative to maximum operating voltages of those components. A driver bias generator selectively applies bias voltages at gates of transistors of a stacked driver structure of an IC to prevent the voltage drop across any given transistor of the stacked driver structure from exceeding a predetermined threshold associated with the maximum operating voltage range of the transistors.

公开(公告)号：US11418187B1

公开(公告)日：2022-08-16

申请号：US17486425

申请日：2021-09-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Ashish Sahu ,  Aniket Bharat Waghide ,  Girish Anathahalli Singrigowda ,  Prasant Kumar Vallur

IPC: H03K5/22 ,  H03K17/22 ,  H03K5/24 ,  H03K3/3565 ,  G06F1/24 ,  G06F1/28

Abstract: A power supply detection circuit for an integrated circuit (IC) includes a reference voltage circuit and a comparator circuit. The reference voltage circuit produces a reference voltage from the supply voltage at a reference voltage node. The comparator circuit includes a first p-type metal oxide semiconductor (PMOS) transistor with a source coupled to a positive supply terminal, a gate receiving the reference voltage, and a drain connected to a comparator output terminal. A first n-type metal oxide semiconductor (NMOS) transistor has a drain connected to the comparator output terminal, a source connected to the negative supply terminal, and a gate receiving a second voltage that varies relative to the supply voltage. A second PMOS transistor has a source coupled to the positive supply terminal, a gate connected to the reference voltage node, and a drain providing the second voltage and coupled to a filter.