公开(公告)号：US20250004828A1

公开(公告)日：2025-01-02

申请号：US18216314

申请日：2023-06-29

Applicant: ADVANCED MICRO DEVICES, INC. ,  XILINX, INC.

Inventor： Mark Unruh Wyse ,  Anthony Thomas Gutierrez ,  Paul Blinzer ,  Samuel Richard Bayliss

IPC: G06F9/48 ,  G06F9/38

Abstract: A processor employs a hardware signal monitor to manage signaling for accelerators. The hardware signal monitor monitors designated memory addresses assigned to accelerator signals. In response to a memory write to one of the designated memory addresses, the hardware signal monitor executes a set of one or more operations (referred to as a callback). The hardware signal monitor thereby enables improved and enhanced signaling features, such as asynchronous signaling between agents, inter-accelerator signaling, and inter-process signaling.

公开(公告)号：US20250004806A1

公开(公告)日：2025-01-02

申请号：US18216310

申请日：2023-06-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Mark Unruh Wyse ,  Anthony Thomas Gutierrez ,  Stephen Alexander Zekany ,  Paul Blinzer

IPC: G06F9/455

Abstract: A processing unit (e.g., a CPU) executes multiple processes, such as multiple virtual machines, wherein each process employs virtual signals and virtual signal monitors to support signaling between the process and one or more accelerators. A hardware signal manager (HSM) assigns each virtual signal to a physical signal of the system and assigns each virtual signal monitor to a physical signal monitor. Based on a process' interactions (e.g., signal operations) with a virtual signal monitor, the HSM executes corresponding interactions at the assigned physical signal monitor. The HSM thus virtualizes the physical signal monitors for the executing processes.

公开(公告)号：US20240385872A1

公开(公告)日：2024-11-21

申请号：US18198981

申请日：2023-05-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Martha Massee Barker ,  Anthony Thomas Gutierrez ,  Mark Unruh Wyse ,  Ali Arda Eker

IPC: G06F9/48

Abstract: In accordance with the described techniques for aggregation and scheduling of accelerator executable tasks, an accelerator device includes a processing element array and a command processor to receive a plurality of fibers each including multiple tasks and dependencies between the multiple tasks. The command processor places a first fiber in a sleep pool based on a first task within the first fiber having an unresolved dependency, and the command processor further places a second fiber in a ready pool based on a second task within the second fiber having a resolved dependency. Based on the second fiber being in the ready pool, the command processor launches the second task to be executed by the processing element array.