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公开(公告)号:US10067710B2
公开(公告)日:2018-09-04
申请号:US15360518
申请日:2016-11-23
Applicant: Advanced Micro Devices, Inc.
Inventor: Joseph L. Greathouse , Christopher D. Erb , Michael G. Collins
Abstract: A processing apparatus is provided that includes a plurality of memory regions each corresponding to a memory address and configured to store data associated with the corresponding memory address. The processing apparatus also includes an accelerated processing device in communication with the memory regions and configured to determine a request to allocate an initial memory buffer comprising a number of contiguous memory regions, create a new memory buffer comprising one or more additional memory regions adjacent to the contiguous memory regions of the initial memory buffer, assign one or more values to the one or more additional memory regions and detect a change to the one or more values at the one or more additional memory regions.
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公开(公告)号:US20180143781A1
公开(公告)日:2018-05-24
申请号:US15360518
申请日:2016-11-23
Applicant: Advanced Micro Devices, Inc.
Inventor: Joseph L. Greathouse , Christopher D. Erb , Michael G. Collins
CPC classification number: G06F3/0647 , G06F3/0619 , G06F3/0656 , G06F3/0685 , G06F9/4443 , G06F9/451 , G06T1/20 , G06T1/60
Abstract: A processing apparatus is provided that includes a plurality of memory regions each corresponding to a memory address and configured to store data associated with the corresponding memory address. The processing apparatus also includes an accelerated processing device in communication with the memory regions and configured to determine a request to allocate an initial memory buffer comprising a number of contiguous memory regions, create a new memory buffer comprising one or more additional memory regions adjacent to the contiguous memory regions of the initial memory buffer, assign one or more values to the one or more additional memory regions and detect a change to the one or more values at the one or more additional memory regions.
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