公开(公告)号：US20190018800A1

公开(公告)日：2019-01-17

申请号：US15650252

申请日：2017-07-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan JAYASENA ,  Brandon K. POTTER ,  Andrew G. KEGEL

IPC: G06F12/14 ,  G06F12/0875 ,  G06F9/48 ,  G06F9/455 ,  G06F9/50 ,  G06F12/10

Abstract: A host processor receives an address translation request from an accelerator, which may be trusted or un-trusted. The address translation request includes a virtual address in a virtual address space that is shared by the host processor and the accelerator. The host processor encrypts a physical address in a host memory indicated by the virtual address in response to the accelerator being permitted to access the physical address. The host processor then provides the encrypted physical address to the accelerator. The accelerator provides memory access requests including the encrypted physical address to the host processor, which decrypts the physical address and selectively accesses a location in the host memory indicated by the decrypted physical address depending upon whether the accelerator is permitted to access the location indicated by the decrypted physical address.

公开(公告)号：US20190163644A1

公开(公告)日：2019-05-30

申请号：US15826061

申请日：2017-11-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Nuwan JAYASENA ,  Yasuko ECKERT

IPC: G06F12/1027 ,  G06F12/128 ,  G06F12/1009

Abstract: A first processor is configured to detect migration of a page from a second memory associated with a second processor to a first memory associated with the first processor or to detect duplication of the page in the first memory and the second memory. The first processor implements a translation lookaside buffer (TLB) and the first processor is configured to insert an entry in the TLB in response to the duplication or the migration of the page. The entry maps a virtual address of the page to a physical address in the first memory and the entry is inserted into the TLB without modifying a corresponding entry in a page table that maps the virtual address of the page to a physical address in the second memory. In some cases, a duplicate translation table (DTT) stores a copy of the entry that is accessed in response to a TLB miss.