公开(公告)号：US20160077981A1

公开(公告)日：2016-03-17

申请号：US14484944

申请日：2014-09-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Andrew G. KEGEL

IPC: G06F13/10 ,  G06F9/455

CPC classification number: G06F13/102 ,  G06F9/4411 ,  G06F9/45558 ,  G06F2009/45579

Abstract: In a virtualized computer system without an IOMMU, all application IO requests must be processed by the guest operating system and by the hypervisor so that addresses are translated (twice) and validated (twice) properly. In a virtualized computer system with an IOMMU containing one “stage” of translation, the peripheral can safely be assigned directly to a guest OS because the IOMMU can be programmed to translate and check addresses issued by the device. As a result, route IO overhead due to hypervisor intervention can be eliminated. In one example, in a virtualized computer system with an IOMMU supporting two “stages” of translation, the peripheral can safely be assigned directly to an application within a guest OS. As a result, route IO overhead due to hypervisor and guest OS processing can be eliminated. This allows an application to achieve higher IO performance.

Abstract translation: 在没有IOMMU的虚拟化计算机系统中，所有应用程序IO请求必须由客户机操作系统和管理程序处理，以便地址被翻译（两次）并且被正确地验证（两次）。 在具有包含翻译“舞台”的IOMMU的虚拟化计算机系统中，可以将外围设备直接分配给客户操作系统，因为IOMMU可被编程为翻译和检查设备发出的地址。 因此，可以消除由管理程序干预导致的路由IO开销。 在一个示例中，在具有支持翻译两个“阶段”的IOMMU的虚拟化计算机系统中，外围设备可以安全地直接分配给客户机OS内的应用。 因此，可以消除由管理程序和客户操作系统处理引起的路由IO开销。 这允许应用程序实现更高的IO性能。

公开(公告)号：US20240119010A1

公开(公告)日：2024-04-11

申请号：US18380954

申请日：2023-10-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Steven RAASCH ,  Andrew G. KEGEL

IPC: G06F12/1009 ,  G06F9/50 ,  G06F11/07 ,  G06F12/02 ,  G06F12/0871 ,  G06F12/0882 ,  G06F12/1027 ,  G06F12/123

CPC classification number: G06F12/1009 ,  G06F9/5016 ,  G06F11/0772 ,  G06F12/0246 ,  G06F12/0871 ,  G06F12/0882 ,  G06F12/1027 ,  G06F12/123

Abstract: A processing system includes a primary processor and a co-processor. The primary processor is couplable to a memory subsystem having at least one memory and operating to execute system software employing memory address translations based on one or more page tables stored in the memory subsystem. The co-processor is likewise couplable to the memory subsystem and operates to perform iterations of a page table walk through one or more page tables maintained for the memory subsystem and to perform one or more page management operations on behalf of the system software based the iterations of the page table walk. The page management operations performed by the co-processor include analytic data aggregation, free list management and page allocation, page migration management, page table error detection, and the like.

公开(公告)号：US20190018800A1

公开(公告)日：2019-01-17

申请号：US15650252

申请日：2017-07-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan JAYASENA ,  Brandon K. POTTER ,  Andrew G. KEGEL

IPC: G06F12/14 ,  G06F12/0875 ,  G06F9/48 ,  G06F9/455 ,  G06F9/50 ,  G06F12/10

Abstract: A host processor receives an address translation request from an accelerator, which may be trusted or un-trusted. The address translation request includes a virtual address in a virtual address space that is shared by the host processor and the accelerator. The host processor encrypts a physical address in a host memory indicated by the virtual address in response to the accelerator being permitted to access the physical address. The host processor then provides the encrypted physical address to the accelerator. The accelerator provides memory access requests including the encrypted physical address to the host processor, which decrypts the physical address and selectively accesses a location in the host memory indicated by the decrypted physical address depending upon whether the accelerator is permitted to access the location indicated by the decrypted physical address.

公开(公告)号：US20170220485A1

公开(公告)日：2017-08-03

申请号：US15491616

申请日：2017-04-19

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Andrew G. KEGEL ,  Anthony Asaro

IPC: G06F12/1081 ,  G06F12/1009 ,  G06F12/1027

CPC classification number: G06F12/1081 ,  G06F12/02 ,  G06F12/1009 ,  G06F12/1027 ,  G06F13/28 ,  G06F2212/1016 ,  G06F2212/2532 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2212/68

Abstract: A device may receive a direct memory access request that identifies a virtual address. The device may determine whether the virtual address is within a particular range of virtual addresses. The device may selectively perform a first action or a second action based on determining whether the virtual address is within the particular range of virtual addresses. The first action may include causing a first address translation algorithm to be performed to translate the virtual address to a physical address associated with a memory device when the virtual address is not within the particular range of virtual addresses. The second action may include causing a second address translation algorithm to be performed to translate the virtual address to the physical address when the virtual address is within the particular range of virtual addresses. The second address translation algorithm may be different from the first address translation algorithm.

公开(公告)号：US20210182206A1

公开(公告)日：2021-06-17

申请号：US16712129

申请日：2019-12-12

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Steven RAASCH ,  Andrew G. KEGEL

IPC: G06F12/1009 ,  G06F12/1027 ,  G06F12/123 ,  G06F12/0882 ,  G06F12/0871 ,  G06F12/02 ,  G06F11/07 ,  G06F9/50

Abstract: A processing system includes a primary processor and a co-processor. The primary processor is couplable to a memory subsystem having at least one memory and operating to execute system software employing memory address translations based on one or more page tables stored in the memory subsystem. The co-processor is likewise couplable to the memory subsystem and operates to perform iterations of a page table walk through one or more page tables maintained for the memory subsystem and to perform one or more page management operations on behalf of the system software based the iterations of the page table walk. The page management operations performed by the co-processor include analytic data aggregation, free list management and page allocation, page migration management, page table error detection, and the like.

公开(公告)号：US20160062911A1

公开(公告)日：2016-03-03

申请号：US14469928

申请日：2014-08-27

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Andrew G. KEGEL ,  Anthony ASARO

IPC: G06F12/10 ,  G06F12/02 ,  G06F13/28

CPC classification number: G06F12/1081 ,  G06F12/02 ,  G06F12/1009 ,  G06F12/1027 ,  G06F13/28 ,  G06F2212/1016 ,  G06F2212/2532 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2212/68

Abstract: A device may receive a direct memory access request that identifies a virtual address. The device may determine whether the virtual address is within a particular range of virtual addresses. The device may selectively perform a first action or a second action based on determining whether the virtual address is within the particular range of virtual addresses. The first action may include causing a first address translation algorithm to be performed to translate the virtual address to a physical address associated with a memory device when the virtual address is not within the particular range of virtual addresses. The second action may include causing a second address translation algorithm to be performed to translate the virtual address to the physical address when the virtual address is within the particular range of virtual addresses. The second address translation algorithm may be different from the first address translation algorithm.

Abstract translation: 设备可以接收标识虚拟地址的直接存储器访问请求。 设备可以确定虚拟地址是否在虚拟地址的特定范围内。 该设备可以基于确定虚拟地址是否在虚拟地址的特定范围内来选择性地执行第一动作或第二动作。 第一动作可以包括当虚拟地址不在虚拟地址的特定范围内时，执行第一地址转换算法来将虚拟地址转换为与存储器设备相关联的物理地址。 第二动作可以包括当虚拟地址在虚拟地址的特定范围内时，执行第二地址转换算法来将虚拟地址转换为物理地址。 第二地址转换算法可能与第一地址转换算法不同。

公开(公告)号：US20140173265A1

公开(公告)日：2014-06-19

申请号：US13720293

申请日：2012-12-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Andrew G. KEGEL

IPC: G06F21/57

CPC classification number: G06F21/575 ,  G06F21/78

Abstract: Embodiments include methods, systems, and computer storage devices directed to identifying that a trusted boot mode (TBM) control bit is set in an input/output memory management unit (IOMMU) and configuring the IOMMU to block a DMA request received by the IOMMU from a peripheral in response to the identifying.

Abstract translation: 实施例包括旨在识别在输入/输出存储器管理单元（IOMMU）中设置可信引导模式（TBM）控制位并且配置IOMMU以阻止由IOMMU接收的DMA请求的方法，系统和计算机存储设备 响应识别的外设。