公开(公告)号：US12204908B2

公开(公告)日：2025-01-21

申请号：US15997344

申请日：2018-06-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Marius Evers ,  Douglas Williams ,  Ashok T. Venkatachar ,  Sudherssen Kalaiselvan

IPC: G06F9/38 ,  G06F9/30

Abstract: A branch predictor predicts a first outcome of a first branch in a first block of instructions. Fetch logic fetches instructions for speculative execution along a first path indicated by the first outcome. Information representing a remainder of the first block is stored in response to the first predicted outcome being taken. In response to the first branch instruction being not taken, the branch predictor is restarted based on the remainder block. In some cases, entries corresponding to second blocks along speculative paths from the first block are accessed using an address of the first block as an index into a branch prediction structure. Outcomes of branch instructions in the second blocks are concurrently predicted using a corresponding set of instances of branch conditional logic and the predicted outcomes are used in combination with the remainder block to restart the branch predictor in response to mispredictions.

公开(公告)号：US10127044B2

公开(公告)日：2018-11-13

申请号：US14522831

申请日：2014-10-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Douglas Williams ,  Sahil Arora ,  Nikhil Gupta ,  Wei-Yu Chen ,  Debjit Das Sarma ,  Marius Evers

IPC: G06F9/38 ,  G06F9/30

Abstract: A processor, a device, and a non-transitory computer readable medium for performing branch prediction in a processor are presented. The processor includes a front end unit. The front end unit includes a level 1 branch target buffer (BTB), a BTB index predictor (BIP), and a level 1 hash perceptron (HP). The BTB is configured to predict a target address. The BIP is configured to generate a prediction based on a program counter and a global history, wherein the prediction includes a speculative partial target address, a global history value, a global history shift value, and a way prediction. The HP is configured to predict whether a branch instruction is taken or not taken.

公开(公告)号：US20150121050A1

公开(公告)日：2015-04-30

申请号：US14522831

申请日：2014-10-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Douglas Williams ,  Sahil Arora ,  Nikhil Gupta ,  Wei-Yu Chen ,  Debjit Das Sarma ,  Marius Evers

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3806 ,  G06F9/30058 ,  G06F9/3848

Abstract: A processor, a device, and a non-transitory computer readable medium for performing branch prediction in a processor are presented. The processor includes a front end unit. The front end unit includes a level 1 branch target buffer (BTB), a BTB index predictor (BIP), and a level 1 hash perceptron (HP). The BTB is configured to predict a target address. The BIP is configured to generate a prediction based on a program counter and a global history, wherein the prediction includes a speculative partial target address, a global history value, a global history shift value, and a way prediction. The HP is configured to predict whether a branch instruction is taken or not taken.

Abstract translation: 提出了一种用于在处理器中执行分支预测的处理器，设备和非暂时性计算机可读介质。 处理器包括前端单元。 前端单元包括1级分支目标缓冲器（BTB），BTB索引预测器（BIP）和1级散列感知器（HP）。 BTB被配置为预测目标地址。 BIP被配置为基于程序计数器和全局历史生成预测，其中预测包括推测性部分目标地址，全局历史值，全局历史偏移值和路径预测。 HP配置为预测是否采用分支指令。