公开(公告)号：US20130205179A1

公开(公告)日：2013-08-08

申请号：US13839621

申请日：2013-03-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Wei-Yu Chen ,  Kevin Badgett ,  Kay Hesse

IPC: G11C29/36

CPC classification number: G11C29/36 ,  G11C29/06 ,  G11C29/28 ,  G11C2029/2602

Abstract: Integrated circuits with memory built-in self test (MBIST) circuitry and methods are disclosed that employ enhanced features. In one aspect of the invention, an integrated circuit is provided having MIBST circuitry configured to serially test multiple arrays of memory elements within a component of the integrated circuit and to also conduct parallel initialization of the serially tested arrays. In another aspect of the invention, the MBST circuitry is used set the memory elements of the arrays to a first state and then to an inverse state during a burn-in operation to maintain each of the two opposing states for a desired time in order to either force a failure of the integrated circuit component or produce a pre-stressed component beyond an infancy stage.

Abstract translation: 具有存储器内置自检（MBIST）电路和方法的集成电路被公开，其采用增强的特征。 在本发明的一个方面，提供了一种集成电路，其具有MBIST电路，其被配置为串行测试集成电路的部件内的多个存储元件阵列，并且还对串行测试阵列进行并行初始化。 在本发明的另一方面，使用MBIST电路将阵列的存储元件设置为第一状态，然后在老化操作期间将其置于反向状态，以将两个相对状态中的每一个保持期望的时间，以便 要么强制集成电路部件的故障或者产生超过初级阶段的预应力部件。

公开(公告)号：US10127044B2

公开(公告)日：2018-11-13

申请号：US14522831

申请日：2014-10-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Douglas Williams ,  Sahil Arora ,  Nikhil Gupta ,  Wei-Yu Chen ,  Debjit Das Sarma ,  Marius Evers

IPC: G06F9/38 ,  G06F9/30

Abstract: A processor, a device, and a non-transitory computer readable medium for performing branch prediction in a processor are presented. The processor includes a front end unit. The front end unit includes a level 1 branch target buffer (BTB), a BTB index predictor (BIP), and a level 1 hash perceptron (HP). The BTB is configured to predict a target address. The BIP is configured to generate a prediction based on a program counter and a global history, wherein the prediction includes a speculative partial target address, a global history value, a global history shift value, and a way prediction. The HP is configured to predict whether a branch instruction is taken or not taken.

公开(公告)号：US20150121050A1

公开(公告)日：2015-04-30

申请号：US14522831

申请日：2014-10-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Douglas Williams ,  Sahil Arora ,  Nikhil Gupta ,  Wei-Yu Chen ,  Debjit Das Sarma ,  Marius Evers

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3806 ,  G06F9/30058 ,  G06F9/3848

Abstract: A processor, a device, and a non-transitory computer readable medium for performing branch prediction in a processor are presented. The processor includes a front end unit. The front end unit includes a level 1 branch target buffer (BTB), a BTB index predictor (BIP), and a level 1 hash perceptron (HP). The BTB is configured to predict a target address. The BIP is configured to generate a prediction based on a program counter and a global history, wherein the prediction includes a speculative partial target address, a global history value, a global history shift value, and a way prediction. The HP is configured to predict whether a branch instruction is taken or not taken.

Abstract translation: 提出了一种用于在处理器中执行分支预测的处理器，设备和非暂时性计算机可读介质。 处理器包括前端单元。 前端单元包括1级分支目标缓冲器（BTB），BTB索引预测器（BIP）和1级散列感知器（HP）。 BTB被配置为预测目标地址。 BIP被配置为基于程序计数器和全局历史生成预测，其中预测包括推测性部分目标地址，全局历史值，全局历史偏移值和路径预测。 HP配置为预测是否采用分支指令。

公开(公告)号：US08639994B2

公开(公告)日：2014-01-28

申请号：US13839621

申请日：2013-03-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Wei-Yu Chen ,  Kevin Badgett ,  Kay Hesse

IPC: G01R31/28

CPC classification number: G11C29/36 ,  G11C29/06 ,  G11C29/28 ,  G11C2029/2602

Abstract: Integrated circuits with memory built-in self test (MBIST) circuitry and methods are disclosed that employ enhanced features. In one aspect of the invention, an integrated circuit is provided having MIBST circuitry configured to serially test multiple arrays of memory elements within a component of the integrated circuit and to also conduct parallel initialization of the serially tested arrays. In another aspect of the invention, the MBST circuitry is used set the memory elements of the arrays to a first state and then to an inverse state during a burn-in operation to maintain each of the two opposing states for a desired time in order to either force a failure of the integrated circuit component or produce a pre-stressed component beyond an infancy stage.

Abstract translation: 具有存储器内置自检（MBIST）电路和方法的集成电路被公开，其采用增强的特征。 在本发明的一个方面，提供了一种集成电路，其具有MBIST电路，其被配置为串行测试集成电路的部件内的多个存储元件阵列，并且还对串行测试阵列进行并行初始化。 在本发明的另一方面，使用MBIST电路将阵列的存储元件设置为第一状态，然后在老化操作期间将其置于反向状态，以将两个相对状态中的每一个保持期望的时间，以便 要么强制集成电路部件的故障或者产生超过初级阶段的预应力部件。