公开(公告)号：US20250130767A1

公开(公告)日：2025-04-24

申请号：US18921401

申请日：2024-10-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Shubh Shah ,  Ashutosh Garg ,  Bin He ,  Michael Mantor ,  Shubra Marwaha ,  Subramaniam Maiyuran

IPC: G06F7/483

Abstract: The disclosed circuit can select micro-operations specifically for converting a value in a first number format to a second number format. The circuit can include micro-operations for various conversions between different number formats, including number formats of different floating-point precisions. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US11720328B2

公开(公告)日：2023-08-08

申请号：US17029836

申请日：2020-09-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Bin He ,  Shubh Shah ,  Michael Mantor

IPC: G06F7/57 ,  G06N3/08 ,  G06F17/16

CPC classification number: G06F7/57 ,  G06F17/16 ,  G06N3/08

Abstract: A parallel processing unit employs an arithmetic logic unit (ALU) having a relatively small footprint, thereby reducing the overall power consumption and circuit area of the processing unit. To support the smaller footprint, the ALU includes multiple stages to execute operations corresponding to a received instruction. The ALU executes at least one operation at a precision indicated by the received instruction, and then reduces the resulting data of the at least one operation to a smaller size before providing the results to another stage of the ALU to continue execution of the instruction.

公开(公告)号：US20250130774A1

公开(公告)日：2025-04-24

申请号：US18395190

申请日：2023-12-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Shubh Shah ,  Ashutosh Garg ,  Bin He ,  Michael Mantor ,  Shubra Marwaha ,  Subramaniam Maiyuran

IPC: G06F7/556 ,  G06F7/483

Abstract: The disclosed circuit can interpret a bit sequence as a value based on one of multiple floating point number formats in a bias mode indicated by a bias mode indicator. The circuit can and perform an operation using the value in the bias mode. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20250130794A1

公开(公告)日：2025-04-24

申请号：US18399659

申请日：2023-12-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Shubh Shah ,  Ashutosh Garg ,  Bin He ,  Michael Mantor ,  Shubra Marwaha ,  Subramaniam Maiyuran

IPC: G06F9/30

Abstract: The disclosed processing circuit can perform an operation with a first operand having a first number format and a second operand having a second number format by directly using the first operand in the first number format and the second operand in the second number format to produce an output result. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20250130769A1

公开(公告)日：2025-04-24

申请号：US18395039

申请日：2023-12-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Shubh Shah ,  Ashutosh Garg ,  Bin He ,  Michael Mantor ,  Shubra Marwaha ,  Subramaniam Maiyuran

IPC: G06F7/499 ,  G06F7/02

Abstract: The disclosed circuit is configured to round a value in a first number format using a random value. Using the rounded value, the circuit can convert the rounded value to a second number format that has a lower precision than a precision of the first number format. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US12217021B2

公开(公告)日：2025-02-04

申请号：US18219268

申请日：2023-07-07

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Bin He ,  Shubh Shah ,  Michael Mantor

IPC: G06F7/57 ,  G06F17/16 ,  G06N3/08

Abstract: A parallel processing unit employs an arithmetic logic unit (ALU) having a relatively small footprint, thereby reducing the overall power consumption and circuit area of the processing unit. To support the smaller footprint, the ALU includes multiple stages to execute operations corresponding to a received instruction. The ALU executes at least one operation at a precision indicated by the received instruction, and then reduces the resulting data of the at least one operation to a smaller size before providing the results to another stage of the ALU to continue execution of the instruction.