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公开(公告)号:US20230033583A1
公开(公告)日:2023-02-02
申请号:US17389925
申请日:2021-07-30
Applicant: Advanced Micro Devices, Inc.
Inventor: XiaoJing Ma , Ling-Ling Wang , Jin Xu , ZengRong Huang , Lina Ma , Wei Shao , LingFei Shi
Abstract: Systems, apparatuses, and methods for implementing a primary input/output (PIO) queue for host and guest operating systems (OS's) are disclosed. A system includes a PIO queue, one or more compute units, and a control unit. The PIO queue is able to store work commands for multiple different types of OS's, including host and guest OS's. The control unit is able to dispatch multiple work commands from multiple OS's to execute concurrently on the compute unit(s). This allows for execution of work commands by different OS's without the processing device(s) having to incur the latency of a world switch.
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公开(公告)号:US20230098742A1
公开(公告)日:2023-03-30
申请号:US17490003
申请日:2021-09-30
Applicant: Advanced Micro Devices, Inc.
Inventor: Ling-Ling Wang , Yuan Du , ZengRong Huang , HaiKun Dong , LingFei Shi , Wei Shao , XiaoJing Ma , Qian Zong , Shenyuan Chen
IPC: G06F1/3296 , G06F13/28 , G06F9/48
Abstract: Apparatuses, systems and methods for performing efficient power management for a processing unit. A processing unit includes two partitions, each assigned to a respective power domain with operating parameters, and each with a respective direct memory access
(DMA) engine. If a controller determines a task type of a received task indicates the task is to be processed by components of the second partition, then the controller assigns the task to the second partition and maintains the operational parameters of the first power domain for the components of the first partition or selects lower performance operational parameters of the first power domain. The processing unit accesses data stored in memory using a DMA engine and operational parameters of the second partition. Additionally, the second partition processes the task using the operational parameters of the second power domain.
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