公开(公告)号：US20230115819A1

公开(公告)日：2023-04-13

申请号：US17499494

申请日：2021-10-12

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： HaiKun Dong ,  Kostantinos Danny Christidis ,  Ling-Ling Wang ,  MinHua Wu ,  Gaojian Cong ,  Rui Wang

IPC: G06F13/16 ,  G06F3/06

Abstract: Systems, apparatuses, and methods for implementing duplicated registers for access by initiators across multiple semiconductor dies are disclosed. A system includes multiple initiators on multiple semiconductor dies of a chiplet processor. One of the semiconductor dies is the master die, and this master die has copies of registers which can be accessed by the multiple initiators on the multiple semiconductor dies. When a given initiator on a given secondary die generates a register access, the register access is routed to the master die and a particular duplicate copy of the register maintained for the given secondary die. From the point of view of software, the multiple semiconductor dies appear as a single die, and the multiple initiators appear as a single initiator. Multiple types of registers can be maintained by the master die, with a flush register being one of the register types.

公开(公告)号：US20240419482A1

公开(公告)日：2024-12-19

申请号：US18336420

申请日：2023-06-16

Applicant: Advanced Micro Devices, Inc.

Inventor： ZengRong Huang ,  Fang Xia ,  HaiKun Dong ,  XiaoJing Ma ,  YongTao Yu ,  YinZhu Xue ,  Alexander Fuad Ashkar ,  Manu Rastogi

IPC: G06F9/48

Abstract: Systems and methods for efficient context switching in multithread processors are disclosed. A processing system comprises a direct memory access module configured to detect a preemption request generated by the scheduling circuit. Responsive to the preemption request, the direct memory access module determines whether execution of a first task from a plurality of tasks needs to be replaced by execution of a second task. When the replacement is necessitated, the module saves a first plurality of registers associated with the first task at a memory location transmitted by the scheduling circuit and queues the second task for execution. The memory location is transmitted by the scheduling circuit as part of the preemption request.

公开(公告)号：US20240370392A1

公开(公告)日：2024-11-07

申请号：US18667752

申请日：2024-05-17

Applicant: Advanced Micro Devices, Inc.

Inventor： HaiKun Dong ,  ZengRong Huang ,  Ling-Ling Wang ,  MinHua Wu ,  Jie Gao ,  RuiHong Liu

IPC: G06F13/24

Abstract: Systems, apparatuses, and methods for implementing a centralized interrupt controller to aggregate interrupts generated across multiple semiconductor dies are disclosed. A system includes multiple interrupt sources on multiple semiconductor dies. A centralized interrupt controller on one of the semiconductor dies receives and aggregates interrupts from the multiple interrupt sources on the multiple semiconductor dies. This facilitates a single transmission point for forwarding the interrupts to the processor and operating system responsible for handling interrupts. Each interrupt source embeds an ID when conveying an interrupt to the interrupt controller. This allows the interrupt controller to differentiate between the interrupt sources and to identify which source generated a given interrupt. The interrupt controller conveys an indication of the source of the interrupt to the processor when forwarding the interrupt to the processor.

公开(公告)号：US20240354268A1

公开(公告)日：2024-10-24

申请号：US18620731

申请日：2024-03-28

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： HaiKun Dong ,  Kostantinos Danny Christidis ,  Ling-Ling Wang ,  MinHua Wu ,  Gaojian Cong ,  Rui Wang

IPC: G06F13/16 ,  G06F3/06

CPC classification number: G06F13/1673 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0688

Abstract: Systems, apparatuses, and methods for implementing duplicated registers for access by initiators across multiple semiconductor dies are disclosed. A system includes multiple initiators on multiple semiconductor dies of a chiplet processor. One of the semiconductor dies is the master die, and this master die has copies of registers which can be accessed by the multiple initiators on the multiple semiconductor dies. When a given initiator on a given secondary die generates a register access, the register access is routed to the master die and a particular duplicate copy of the register maintained for the given secondary die. From the point of view of software, the multiple semiconductor dies appear as a single die, and the multiple initiators appear as a single initiator. Multiple types of registers can be maintained by the master die, with a flush register being one of the register types.

公开(公告)号：US11989144B2

公开(公告)日：2024-05-21

申请号：US17389994

申请日：2021-07-30

Applicant: Advanced Micro Devices, Inc.

Inventor： HaiKun Dong ,  ZengRong Huang ,  Ling-Ling Wang ,  MinHua Wu ,  Jie Gao ,  RuiHong Liu

IPC: G06F13/24

CPC classification number: G06F13/24

Abstract: Systems, apparatuses, and methods for implementing a centralized interrupt controller to aggregate interrupts generated across multiple semiconductor dies are disclosed. A system includes multiple interrupt sources on multiple semiconductor dies. A centralized interrupt controller on one of the semiconductor dies receives and aggregates interrupts from the multiple interrupt sources on the multiple semiconductor dies. This facilitates a single transmission point for forwarding the interrupts to the processor and operating system responsible for handling interrupts. Each interrupt source embeds an ID when conveying an interrupt to the interrupt controller. This allows the interrupt controller to differentiate between the interrupt sources and to identify which source generated a given interrupt. The interrupt controller conveys an indication of the source of the interrupt to the processor when forwarding the interrupt to the processor.

公开(公告)号：US20230098742A1

公开(公告)日：2023-03-30

申请号：US17490003

申请日：2021-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Ling-Ling Wang ,  Yuan Du ,  ZengRong Huang ,  HaiKun Dong ,  LingFei Shi ,  Wei Shao ,  XiaoJing Ma ,  Qian Zong ,  Shenyuan Chen

IPC: G06F1/3296 ,  G06F13/28 ,  G06F9/48

Abstract: Apparatuses, systems and methods for performing efficient power management for a processing unit. A processing unit includes two partitions, each assigned to a respective power domain with operating parameters, and each with a respective direct memory access
(DMA) engine. If a controller determines a task type of a received task indicates the task is to be processed by components of the second partition, then the controller assigns the task to the second partition and maintains the operational parameters of the first power domain for the components of the first partition or selects lower performance operational parameters of the first power domain. The processing unit accesses data stored in memory using a DMA engine and operational parameters of the second partition. Additionally, the second partition processes the task using the operational parameters of the second power domain.

公开(公告)号：US20230034539A1

公开(公告)日：2023-02-02

申请号：US17389994

申请日：2021-07-30

Applicant: Advanced Micro Devices, Inc.

Inventor： HaiKun Dong ,  ZengRong Huang ,  Ling-Ling Wang ,  MinHua Wu ,  Jie Gao ,  RuiHong Liu

IPC: G06F13/24

Abstract: Systems, apparatuses, and methods for implementing a centralized interrupt controller to aggregate interrupts generated across multiple semiconductor dies are disclosed. A system includes multiple interrupt sources on multiple semiconductor dies. A centralized interrupt controller on one of the semiconductor dies receives and aggregates interrupts from the multiple interrupt sources on the multiple semiconductor dies. This facilitates a single transmission point for forwarding the interrupts to the processor and operating system responsible for handling interrupts. Each interrupt source embeds an ID when conveying an interrupt to the interrupt controller. This allows the interrupt controller to differentiate between the interrupt sources and to identify which source generated a given interrupt. The interrupt controller conveys an indication of the source of the interrupt to the processor when forwarding the interrupt to the processor.