公开(公告)号：US20240296128A1

公开(公告)日：2024-09-05

申请号：US18116543

申请日：2023-03-02

Applicant: Advanced Micro Devices, Inc.

Inventor： Wei Sheng

IPC: G06F12/1027 ,  G06F12/02 ,  G06F13/16

CPC classification number: G06F12/1027 ,  G06F12/0292 ,  G06F13/1626

Abstract: An input/output memory management unit includes a control logic circuit and a device table entry valid bit array. The control logic circuit provides physical addresses in response to virtual addresses of memory access requests from a plurality of input/output devices. The device table entry valid bit array stores a plurality of valid bits corresponding to different ones of the plurality of input/output devices. The control logic circuit accesses a first valid bit corresponding to a first input/output device from the device table entry valid bit array, and selectively accesses a device table in a system memory in response to a state of the valid bit.