公开(公告)号：US20240324247A1

公开(公告)日：2024-09-26

申请号：US18474111

申请日：2023-09-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Samuel Naffziger ,  William George En ,  John Wuu

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L24/08 ,  H01L25/18 ,  H01L25/50 ,  H01L23/5286 ,  H01L24/06 ,  H01L2224/06181 ,  H01L2224/08145

Abstract: A method for die pair partitioning can include providing a circuit die that has a metal stack and that includes a majority of logic transistors of an integrated circuit. The method can also include providing one or more additional circuit die that have one or more additional metal stacks of which at least one is connected to the metal stack of the circuit die and a majority of static random access memory and analog devices of the integrated circuit. The method can further include connecting at least one of the one or more additional metal stacks to the metal stack of the circuit die. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20240321706A1

公开(公告)日：2024-09-26

申请号：US18474151

申请日：2023-09-25

Applicant: Advanced Micro Devices, Inc.

Inventor： William George En ,  Samuel Naffziger ,  Regina T. Schmidt ,  Omar Zia ,  John Wuu

IPC: H01L23/498 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/49827 ,  H01L23/481 ,  H01L23/49816 ,  H01L25/0657 ,  H01L2225/06541

Abstract: A method for implementing shared metal connectivity between 3D stacked circuit dies can include providing a first circuit die having a first metal stack. The method can additionally include providing a second circuit die having a second metal stack, wherein at least one metal layer of the second metal stack is utilized by both the first circuit die and the second circuit die. The method can also include connecting the second metal stack to the first metal stack of the first circuit die. Various other methods, systems, and computer-readable media are also disclosed.