PEAK ELECTRICAL CURRENT CONTROL OF SOC OR APU WITH MULTIPLE PROCESSOR CORES AND MULTIPLE GRAPHIC COMPUTE UNITS

    公开(公告)号:US20230205304A1

    公开(公告)日:2023-06-29

    申请号:US17563788

    申请日:2021-12-28

    CPC classification number: G06F1/3287 G06F1/3206

    Abstract: A system and method for efficient power management of an integrated circuit are described. In various implementations, a computing system includes an integrated circuit, multiple voltage regulators, and circuitry that detects when current drawn from a power rail from one of the multiple voltage regulators exceeds a limit. Upon detection, a single global alarm signal is asserted and conveyed to the integrate circuit. The integrated circuit includes at least a first group of functional blocks sharing a first power rail and a second group of functional blocks sharing a second power rail. When the global alarm signal is asserted, the functional blocks of the first group and the second group perform steps to immediately reduce power consumption. In order to maintain performance and satisfy a quality of service (QoS) parameter, a power management controller of the integrated circuit reassigns power limits shortly thereafter.

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