公开(公告)号：US20230205304A1

公开(公告)日：2023-06-29

申请号：US17563788

申请日：2021-12-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Xiuting C. Man ,  Xiaojie He ,  Michael Leonard Golden ,  Richard M. Born

IPC: G06F1/3287 ,  G06F1/3206

CPC classification number: G06F1/3287 ,  G06F1/3206

Abstract: A system and method for efficient power management of an integrated circuit are described. In various implementations, a computing system includes an integrated circuit, multiple voltage regulators, and circuitry that detects when current drawn from a power rail from one of the multiple voltage regulators exceeds a limit. Upon detection, a single global alarm signal is asserted and conveyed to the integrate circuit. The integrated circuit includes at least a first group of functional blocks sharing a first power rail and a second group of functional blocks sharing a second power rail. When the global alarm signal is asserted, the functional blocks of the first group and the second group perform steps to immediately reduce power consumption. In order to maintain performance and satisfy a quality of service (QoS) parameter, a power management controller of the integrated circuit reassigns power limits shortly thereafter.

公开(公告)号：US09575553B2

公开(公告)日：2017-02-21

申请号：US14576924

申请日：2014-12-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Seng Oon Toh ,  Edward J. McLellan ,  Stephen V. Kosonocky ,  Michael Leonard Golden ,  Samuel D. Naffziger

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/04 ,  G06F1/3206 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/172

Abstract: A processor employs a set of replica paths at a processor to determine an operating frequency and voltage for the processor. The replica paths each represent one or more circuit paths at a functional module of the processor. The delays at the replica paths are normalized to increase the likelihood that the replica paths accurately represent the behavior of the circuit paths of the functional module. After normalization, a distribution of delay values is generated by varying, at each replica path, the delay at an output node of the replica path until a mismatch is detected between a signal at the output node of the replica path and the delayed representation of the signal. The resulting distribution of delay values can then be adjusted based on variations in reference voltages at the replica paths to account for potential distribution errors resulting from the reference voltage variations.

Abstract translation: 处理器在处理器处采用一组复制路径来确定处理器的工作频率和电压。 复制路径各自表示处理器的功能模块处的一个或多个电路路径。 复制路径上的延迟被归一化以增加复制路径准确地表示功能模块的电路路径的行为的可能性。 在归一化之后，通过在每个复制路径处改变复制路径的输出节点处的延迟，直到在复制路径的输出节点处的信号与在复制路径的延迟表示之间检测到不匹配来生成延迟值的分布 信号。 然后可以基于复制路径上的参考电压的变化来调整所得到的延迟值分布，以考虑由参考电压变化导致的电位分布误差。

公开(公告)号：US20160179186A1

公开(公告)日：2016-06-23

申请号：US14576924

申请日：2014-12-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Seng Oon Toh ,  Edward J. McLellan ,  Stephen V. Kosonocky ,  Michael Leonard Golden ,  Samuel D. Naffziger

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/04 ,  G06F1/3206 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/172

Abstract: A processor employs a set of replica paths at a processor to determine an operating frequency and voltage for the processor. The replica paths each represent one or more circuit paths at a functional module of the processor. The delays at the replica paths are normalized to increase the likelihood that the replica paths accurately represent the behavior of the circuit paths of the functional module. After normalization, a distribution of delay values is generated by varying, at each replica path, the delay at an output node of the replica path until a mismatch is detected between a signal at the output node of the replica path and the delayed representation of the signal. The resulting distribution of delay values can then be adjusted based on variations in reference voltages at the replica paths to account for potential distribution errors resulting from the reference voltage variations.

Abstract translation: 处理器在处理器处采用一组复制路径来确定处理器的工作频率和电压。 复制路径各自表示处理器的功能模块处的一个或多个电路路径。 复制路径上的延迟被归一化以增加复制路径准确地表示功能模块的电路路径的行为的可能性。 在归一化之后，通过在每个复制路径处改变复制路径的输出节点处的延迟，直到在复制路径的输出节点处的信号与在复制路径的延迟表示之间检测到不匹配来生成延迟值的分布 信号。 然后可以基于复制路径上的参考电压的变化来调整所得到的延迟值分布，以考虑由参考电压变化导致的电位分布误差。