公开(公告)号：US11036658B2

公开(公告)日：2021-06-15

申请号：US16249649

申请日：2019-01-16

申请人： Advanced Micro Devices, Inc. ,  ATI Technologies ULC

发明人： Vydhyanathan Kalyanasundharam ,  Philip Ng ,  Alexander J Branover ,  Kevin M. Lepak

IPC分类号： G06F13/16 ,  G06F9/38 ,  G06F9/50 ,  G06F9/48

摘要： Systems, methods, and port controller designs employ a light-weight memory protocol. A light-weight memory protocol controller is selectively coupled to a Cache Coherent Interconnect for Accelerators (CCIX) port. Over an on-chip interconnect fabric, the light-weight protocol controller receives memory access requests from a processor and, in response, transmits associated memory access requests to an external memory through the CCIX port using only a proper subset of CCIX protocol memory transactions types including non-cacheable transactions and non-snooping transactions. The light-weight memory protocol controller is selectively uncoupled from the CCIX port and a remote coherent slave controller is coupled in its place. The remote coherent slave controller receives memory access requests and, in response, transmits associated memory access requests to a memory module through the CCIX port using cacheable CCIX protocol memory transaction types.