公开(公告)号：US20250079276A1

公开(公告)日：2025-03-06

申请号：US18241140

申请日：2023-08-31

Applicant: Advanced Micro Devices, Inc. ,  XILINX, INC.

Inventor： Manish DUBEY ,  Frank Peter LAMBRECHT ,  Brett P. WILKERSON ,  Deepak Vasant KULKARNI ,  Hemanth Kumar DHAVALESWARAPU ,  Priyal SHAH

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/043 ,  H01L25/065 ,  H05K1/14

Abstract: Disclosed herein is a chip package assembly that includes a package substrate coupled with an integrated circuit die, a stiffener attached to a top surface of the package substrate, and a connector assembly integrated with the stiffener. Both the connector assembly and the stiffener are disposed at a peripheral area of the top surface. The connector assembly includes a bracket and a connector. The connector is configured to connect with one or more optical cables or electrical connectors. The bracket may be formed by a cavity in the stiffener. The bracket may be attached to the top surface of the package substrate. The stiffener may be coupled with the bracket directly or via the connector. Additionally, a frame coupled to the stiffener or a PCB board may be used to secure the bracket in place.

公开(公告)号：US20250118706A1

公开(公告)日：2025-04-10

申请号：US18377280

申请日：2023-10-05

Applicant: Advanced Micro Devices, Inc.

Inventor： Manish DUBEY ,  Arsalan ALAM ,  Hemanth Kumar DHAVALESWARAPU ,  Chandra Sekhar MANDALAPU ,  Sriram CHANDRASEKARAN

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/36 ,  H01L23/538 ,  H01L25/00

Abstract: A chip package and method for fabricating the same are provided that include a IC dies bonded to a thermal carrier having a plurality of metallic pillars. In one example, a chip package includes an interconnect routing structure and a first die disposed on a first surface of the interconnect routing structure. The first die has a circuitry connected to a circuitry of the interconnect routing structure. The chip package also includes a second die at least partially disposed over the first die. The second die has a circuitry connected to the circuitry of the first die. A thermal carrier is bonded on the second die. At least one of the thermal carrier, the first die, or the second die includes a plurality of metallic pillars configured to transfer heat, wherein the plurality of metallic pillars are electrically floating.

公开(公告)号：US20240332098A1

公开(公告)日：2024-10-03

申请号：US18128940

申请日：2023-03-30

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Suming HU ,  Roden TOPACIO ,  Manish DUBEY ,  Jianguo LI

IPC: H01L23/051 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/051 ,  H01L21/563 ,  H01L23/3114

Abstract: A chip package includes a package substrate, an integrated circuit (IC) die disposed on the package substrate, and a lid assembly disposed over the IC die. The lid assembly includes a top plate having a lower surface facing the IC die and an outer shoulder. The lid assembly also includes a retainer having a lower surface secured to the package substrate and an inner shoulder retaining to the outer shoulder. The inner shoulder is configured to limit upward movement of the top plate, and expansion of the retainer is decoupled from expansion of the top plate.

公开(公告)号：US20250167192A1

公开(公告)日：2025-05-22

申请号：US18518184

申请日：2023-11-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Arsalan ALAM ,  Chandra Sekhar MANDALAPU ,  Liwei WANG ,  Omkar Deepak GUPTE ,  Anadi SRIVASTAVA ,  Sai VADLAMANI ,  Sri Ranga Sai BOYAPATI ,  Manish DUBEY

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

Abstract: Disclosed herein is an integrated circuit die stack and an integrated circuit die package assembly having the integrated circuit die stack. The integrated circuit die stack includes first plurality of integrated circuit dice disposed in a first tier of the die stack, and the first plurality of integrated circuit dice include a first integrated circuit die and a bridge die. The integrated circuit die stack further includes a second plurality of integrated circuit dice disposed in a second tier of the die stack, and the second plurality of integrated circuit dice are stacked vertically above the first plurality of the integrated circuit dice of the first tier and include a second integrated circuit die and a third integrated circuit die. The bridge die couples with both the second integrated circuit die and the third integrated circuit die.