-
公开(公告)号：US20150347090A1
公开(公告)日：2015-12-03
申请号：US14824691
申请日：2015-08-12
Applicant: Advanced Micro Devices, Inc.
Inventor： Scott Hilker
CPC classification number: G06F7/4876 , G06F5/01 , G06F5/012 , G06F7/483 , G06F7/485 , G06F7/523 , G06F7/5443 , G06F2205/003 , G06F2207/382
Abstract: A processing device is provided that includes a first, second and third precision operation circuit. The processing device further includes a shared, bit-shifting circuit that is communicatively coupled to the first, second and third precision operation circuits. A method is also provided for multiplying a first and second binary number including adding a first exponent value associated with the first binary number to a second exponent value associated with the second binary number and multiplying a first mantissa value associated with the first binary number to a second mantissa value associated with the second binary number. The method includes performing the exponent adding and mantissa multiplying substantially in parallel. The method further includes performing at least one of adding or subtracting a third binary number to the product. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus.
Abstract translation: 提供一种包括第一，第二和第三精密运算电路的处理装置。 处理装置还包括通信地耦合到第一，第二和第三精密运算电路的共享的位移电路。 还提供了一种用于将第一和第二二进制数相乘的方法，包括将与第一二进制数相关联的第一指数值与与第二二进制数相关联的第二指数值相加，并将与第一二进制数相关联的第一尾数值与 与第二二进制数相关联的第二尾数值。 该方法包括基本并行地执行指数加法和尾数乘法。 该方法还包括执行向产品添加或减去第三二进制数中的至少一个。 还提供了一种用数据编码的计算机可读存储设备，用于使制造设备适配以创建设备。
-
公开(公告)号：US09557963B2
公开(公告)日：2017-01-31
申请号：US14824691
申请日：2015-08-12
Applicant: Advanced Micro Devices, Inc.
Inventor： Scott Hilker
CPC classification number: G06F7/4876 , G06F5/01 , G06F5/012 , G06F7/483 , G06F7/485 , G06F7/523 , G06F7/5443 , G06F2205/003 , G06F2207/382
Abstract: A processing device is provided that includes a first, second and third precision operation circuit. The processing device further includes a shared, bit-shifting circuit that is communicatively coupled to the first, second and third precision operation circuits. A method is also provided for multiplying a first and second binary number including adding a first exponent value associated with the first binary number to a second exponent value associated with the second binary number and multiplying a first mantissa value associated with the first binary number to a second mantissa value associated with the second binary number. The method includes performing the exponent adding and mantissa multiplying substantially in parallel. The method further includes performing at least one of adding or subtracting a third binary number to the product. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus.
Abstract translation: 提供一种包括第一，第二和第三精密运算电路的处理装置。 处理装置还包括通信地耦合到第一，第二和第三精密运算电路的共享的位移电路。 还提供了一种用于将第一和第二二进制数相乘的方法，包括将与第一二进制数相关联的第一指数值与与第二二进制数相关联的第二指数值相加，并将与第一二进制数相关联的第一尾数值与 与第二二进制数相关联的第二尾数值。 该方法包括基本并行地执行指数加法和尾数乘法。 该方法还包括执行向产品添加或减去第三二进制数中的至少一个。 还提供了一种用数据编码的计算机可读存储设备，用于使制造设备适配以创建设备。
-
公开(公告)号：US20170147288A1
公开(公告)日：2017-05-25
申请号：US15391470
申请日：2016-12-27
Applicant: Advanced Micro Devices, Inc.
Inventor： Scott Hilker
CPC classification number: G06F7/4876 , G06F5/01 , G06F5/012 , G06F7/483 , G06F7/485 , G06F7/523 , G06F7/5443 , G06F2205/003 , G06F2207/382
Abstract: A processing device is provided that includes a first, second and third precision operation circuit. The processing device further includes a shared, bit-shifting circuit that is communicatively coupled to the first, second and third precision operation circuits. A method is also provided for multiplying a first and second binary number including adding a first exponent value associated with the first binary number to a second exponent value associated with the second binary number and multiplying a first mantissa value associated with the first binary number to a second mantissa value associated with the second binary number. The method includes performing the exponent adding and mantissa multiplying substantially in parallel. The method further includes performing at least one of adding or subtracting a third binary number to the product. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus.
-
公开(公告)号：US20130282784A1
公开(公告)日：2013-10-24
申请号：US13921316
申请日：2013-06-19
Applicant: Advanced Micro Devices,Inc.
Inventor： David S. Oliver , Debjit Das Sarma , Scott Hilker
IPC: G06F7/483
CPC classification number: G06F7/483 , G06F7/49942 , G06F7/5443
Abstract: A device and methods are disclosed for communicating an unrounded result from one arithmetic calculation for use in a second, subsequent calculation. For example, an unrounded result of a first calculation can be forwarded to provide a multiplier, a multiplicand or an addend operand for the subsequent operation. The operand can be forwarded to the input of the same fused multiply addition module (FMAM) that supplied the result, or to another FMAM, and do so without regard to the precision of the forwarded operand, the precision of the subsequent operation, or the native precision of the FMAM.
Abstract translation: 公开了一种用于传送来自一个算术计算的未包围结果以用于第二次后续计算的装置和方法。 例如，可以转发第一次计算的未包围的结果以提供用于后续操作的乘法器，被乘数或加数操作数。 操作数可以转发给提供结果的相同的融合乘法加法模块（FMAM）的输入，或转发给另一个FMAM，并且不考虑转发操作数的精度，后续操作的精度，或者 FMAM的本机精度。
-
-
-
Search Results
4
records
(took 0.016 seconds)
