公开(公告)号：US11867720B2

公开(公告)日：2024-01-09

申请号：US17099610

申请日：2020-11-16

Applicant: Advantest Corporation

Inventor： Eddy Wayne Chow

IPC: G01R1/04 ,  G01R31/319 ,  G01R31/3185

CPC classification number: G01R1/0441 ,  G01R31/31905 ,  G01R31/318519

Abstract: Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a test system configuration adapter includes a tester side socket, a break out pin, and a device under test (DUT) side slot. The tester side socket is configured to couple with a test equipment socket. The break out pin is configured to couple with the supplemental equipment. The DUT side slot is configured to couple with the tester side socket, the break out pin, and a DUT. The test system configuration adapter is configured to enable communication between test equipment coupled to the test equipment socket and supplemental equipment coupled to the breakout pin while the DUT remains coupled to the DUT side slot. The breakout pin and tester side socket can be selectively coupled to the DUT side slot.

公开(公告)号：US12079098B2

公开(公告)日：2024-09-03

申请号：US17135790

申请日：2020-12-28

Applicant: Advantest Corporation

Inventor： Mei-Mei Su ,  Eddy Wayne Chow ,  Edmundo De La Puente

IPC: G06F11/273 ,  G01R31/317 ,  G06F13/42

CPC classification number: G06F11/2736 ,  G01R31/31724 ,  G06F13/4282 ,  G06F2213/0026 ,  G06F2213/0028

Abstract: An automated test equipment (ATE) system comprises a system controller communicatively coupled to a tester processor, where the system controller is operable to transmit instructions to the tester processor, and where the tester processor is operable to generate commands and data from the instructions for coordinating testing of a plurality of devices under test (DUTs). The apparatus also comprises an FPGA programmed to support a first protocol communicatively coupled to the tester processor comprising at least one hardware accelerator circuit operable to internally generate commands and data transparently from the tester processor for testing a DUT of the plurality of DUTs. Further, the apparatus comprises a bus adapter comprising a protocol converter module operable to convert signals associated with the first protocol received from the FPGA to signals associated with a second protocol prior to transmitting the signals to the DUT, wherein the DUT communicates using the second protocol.

公开(公告)号：US11108640B2

公开(公告)日：2021-08-31

申请号：US16227479

申请日：2018-12-20

Applicant: Advantest Corporation

Inventor： Eddy Wayne Chow

IPC: H04L12/24 ,  H04L29/08 ,  G06F13/42

Abstract: A method for controlling devices in a de-centralized storage environment comprises partitioning a plurality of devices in a network into a plurality of super-cells, wherein each super-cell comprises a subset of the plurality of devices. For each super-cell, a system controller is configured to nominate a device in the super-cell as a nucleus device, wherein the nucleus device in the super-cell controls member devices in the super-cell. The system controller is further configured to transmit commands associated with a specific task to the nucleus device and receive information from the nucleus device regarding performance of the specific task, wherein the information comprises information aggregated from the member devices of the super-cell associated with a performance of a respective portion of the specific task.