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    Per Thread Cacheline Allocation Mechanism in Shared Partitioned Caches in Multi-Threaded Processors
    3.
    发明申请
    Per Thread Cacheline Allocation Mechanism in Shared Partitioned Caches in Multi-Threaded Processors 有权
    多线程处理器中共享分区缓存中的每线程Cacheline分配机制

    公开(公告)号：US20130304994A1

    公开(公告)日：2013-11-14

    申请号：US13466359

    申请日：2012-05-08

    申请人： Christopher Edward Koob ,  Ajay Anant Ingle ,  Lucian Codrescu ,  Suresh K. Venkumahanti

    发明人： Christopher Edward Koob ,  Ajay Anant Ingle ,  Lucian Codrescu ,  Suresh K. Venkumahanti

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0842 ,  G06F12/0848 ,  G06F12/0864

    摘要： Systems and methods for allocation of cache lines in a shared partitioned cache of a multi-threaded processor. A memory management unit is configured to determine attributes associated with an address for a cache entry associated with a processing thread to be allocated in the cache. A configuration register is configured to store cache allocation information based on the determined attributes. A partitioning register is configured to store partitioning information for partitioning the cache into two or more portions. The cache entry is allocated into one of the portions of the cache based on the configuration register and the partitioning register.

    摘要翻译： 用于在多线程处理器的共享分区高速缓存中分配高速缓存行的系统和方法。 存储器管理单元被配置为确定与要在高速缓存中分配的处理线程相关联的高速缓存条目的地址相关联的属性。 配置寄存器被配置为基于所确定的属性来存储高速缓存分配信息。 分区寄存器被配置为存储用于将高速缓存分割成两个或更多个部分的分区信息。 基于配置寄存器和分区寄存器，缓存条目被分配到高速缓存的一部分中。

    System and Method of Processing Hierarchical Very Long Instruction Packets
    4.
    发明申请
    System and Method of Processing Hierarchical Very Long Instruction Packets 有权
    处理分层超长指令包的系统和方法

    公开(公告)号：US20110219212A1

    公开(公告)日：2011-09-08

    申请号：US12716359

    申请日：2010-03-03

    申请人： Lucian Codrescu ,  Erich James Plondke ,  Ajay Anant Ingle ,  Suresh K. Venkumahanti ,  Charles Joseph Tabony

    发明人： Lucian Codrescu ,  Erich James Plondke ,  Ajay Anant Ingle ,  Suresh K. Venkumahanti ,  Charles Joseph Tabony

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3853 ,  G06F9/30149

    摘要： A system and method of processing a hierarchical very long instruction word (VLIW) packet is disclosed. In a particular embodiment, a method of processing instructions is disclosed. The method includes receiving a hierarchical VLIW packet of instructions and decoding an instruction from the packet to determine whether the instruction is a single instruction or whether the instruction includes a subpacket that includes a plurality of sub-instructions. The method also includes, in response to determining that the instruction includes the subpacket, executing each of the sub-instructions.

    摘要翻译： 公开了一种处理分级非常长的指令字（VLIW）分组的系统和方法。 在特定实施例中，公开了一种处理指令的方法。 该方法包括：接收分层VLIW指令分组，并对来自分组的指令进行解码，以确定该指令是单个指令还是指令是否包括包含多个子指令的子分组。 响应于确定该指令包括子分组，该方法还包括执行每个子指令。

    System and Method of Executing Instructions in a Multi-Stage Data Processing Pipeline
    5.
    发明申请
    System and Method of Executing Instructions in a Multi-Stage Data Processing Pipeline 有权
    多级数据处理管道中执行指令的系统和方法

    公开(公告)号：US20090070602A1

    公开(公告)日：2009-03-12

    申请号：US11850940

    申请日：2007-09-06

    申请人： Ajay Anant Ingle ,  Lucian Codrescu ,  Suresh K. Venkumahanti

    发明人： Ajay Anant Ingle ,  Lucian Codrescu ,  Suresh K. Venkumahanti

    IPC分类号： G06F9/30 ,  G06F1/26

    CPC分类号： G06F9/3851 ,  G06F9/3867

    摘要： A device is disclosed that includes an instruction execution pipeline having multiple stages for executing an instruction. The device also includes a control logic circuit coupled to the instruction execution pipeline. The control logic circuit is adapted to skip at least one stage of the instruction execution pipeline during execution of the instruction. The control logic circuit is also adapted to execute at least one non-skipped stage during execution of the decoded instruction.

    摘要翻译： 公开了一种包括具有用于执行指令的多个级的指令执行流水线的装置。 该装置还包括耦合到指令执行管线的控制逻辑电路。 控制逻辑电路适于在执行指令期间跳过指令执行流水线的至少一个级。 控制逻辑电路还适于在执行解码指令期间执行至少一个非跳过级。

    System and method of executing instructions in a multi-stage data processing pipeline
    7.
    发明授权
    System and method of executing instructions in a multi-stage data processing pipeline 有权
    在多级数据处理流水线中执行指令的系统和方法

    公开(公告)号：US08868888B2

    公开(公告)日：2014-10-21

    申请号：US11850940

    申请日：2007-09-06

    申请人： Ajay Anant Ingle ,  Lucian Codrescu ,  Suresh K. Venkumahanti

    发明人： Ajay Anant Ingle ,  Lucian Codrescu ,  Suresh K. Venkumahanti

    IPC分类号： G06F15/00 ,  G06F9/44 ,  G06F9/00 ,  G06F7/38 ,  G06F9/38

    CPC分类号： G06F9/3851 ,  G06F9/3867

    摘要： A device is disclosed that includes an instruction execution pipeline having multiple stages for executing an instruction. The device also includes a control logic circuit coupled to the instruction execution pipeline. The control logic circuit is adapted to skip at least one stage of the instruction execution pipeline during execution of the instruction. The control logic circuit is also adapted to execute at least one non-skipped stage during execution of the decoded instruction.

    摘要翻译： 公开了一种包括具有用于执行指令的多个级的指令执行流水线的装置。 该装置还包括耦合到指令执行管线的控制逻辑电路。 控制逻辑电路适于在执行指令期间跳过指令执行流水线的至少一个级。 控制逻辑电路还适于在执行解码指令期间执行至少一个非跳过级。

    Methods and Apparatus for Constant Extension in a Processor
    9.
    发明申请
    Methods and Apparatus for Constant Extension in a Processor 审中-公开
    处理器中恒定扩展的方法和装置

    公开(公告)号：US20120284489A1

    公开(公告)日：2012-11-08

    申请号：US13155565

    申请日：2011-06-08

    申请人： Erich James Plondke ,  Lucian Codrescu ,  Charles Joseph Tabony ,  Suresh K. Venkumahanti ,  Ajay Anant Ingle

    发明人： Erich James Plondke ,  Lucian Codrescu ,  Charles Joseph Tabony ,  Suresh K. Venkumahanti ,  Ajay Anant Ingle

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30192 ,  G06F9/30167

    摘要： Programs often require constants that cannot be encoded in a native instruction format, such as 32-bits. To provide an extended constant, an instruction packet is formed with constant extender information and a target instruction. The constant extender information encoded as a constant extender instruction provides a first set of constant bits, such as 26-bits for example, and the target instruction provides a second set of constant bits, such as 6-bits. The first set of constant bits are combined with the second set of constant bits to generate an extended constant for execution of the target instruction. The extended constant may be used as an extended source operand, an extended address for memory access instructions, an extended address for branch type of instructions, and the like. Multiple constant extender instructions may be used together to provide larger constants than can be provided by a single extension instruction.

    摘要翻译： 程序通常需要不能以本机指令格式编码的常量，例如32位。 为了提供扩展常数，形成具有恒定扩展器信息和目标指令的指令包。 编码为恒定扩展器指令的恒定扩展器信息提供第一组常量位，例如26位，目标指令提供第二组常数位，例如6位。 第一组常数位与第二组常数位组合以产生用于执行目标指令的扩展常数。 扩展常数可以用作扩展源操作数，存储器访问指令的扩展地址，分支类型的指令的扩展地址等。 多个恒定扩展器指令可以一起使用以提供比单个扩展指令可以提供的更大的常数。