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1.发明授权System and method for generating and using predicates within a single instruction packet 有权用于在单个指令包内生成和使用谓词的系统和方法公开(公告)号：US08990543B2
公开(公告)日：2015-03-24
申请号：US12045825
申请日：2008-03-11
申请人： Lucian Codrescu , Robert Allan Lester , Charles Joseph Tabony , Erich James Plondke , Mao Zeng , Suresh Venkumahanti , Ajay Anant Ingle
发明人： Lucian Codrescu , Robert Allan Lester , Charles Joseph Tabony , Erich James Plondke , Mao Zeng , Suresh Venkumahanti , Ajay Anant Ingle
CPC分类号： G06F9/3853 , G06F9/30036 , G06F9/30069 , G06F9/3826 , G06F9/3828 , G06F9/3889
摘要： In a particular embodiment, a method is disclosed that includes receiving an instruction packet including a first instruction and a second instruction that is dependent on the first instruction at a processor having a plurality of parallel execution pipelines, including a first execution pipeline and a second execution pipeline. The method further includes executing in parallel at least a portion of the first instruction and at least a portion of the second instruction. The method also includes selectively committing a second result of executing the at least a portion of the second instruction with the second execution pipeline based on a first result related to execution of the first instruction with the first execution pipeline.
摘要翻译： 在特定实施例中，公开了一种方法，其包括在具有多个并行执行流水线的处理器处接收包括依赖于第一指令的第一指令和第二指令的指令分组，所述处理器包括第一执行流水线和第二执行 管道。 该方法还包括并行地执行第一指令的至少一部分和第二指令的至少一部分。 该方法还包括基于与第一执行流水线执行第一指令相关的第一结果，选择性地提交执行具有第二执行流水线的第二指令的至少一部分的第二结果。
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公开(公告)号：US20130086360A1
公开(公告)日：2013-04-04
申请号：US13249284
申请日：2011-09-30
IPC分类号： G06F9/312
CPC分类号： G06F9/3004 , G06F9/30032 , G06F9/30043
摘要： An instruction identifies a register and a memory location. Upon execution of the instruction by a processor, an item is loaded from the memory location and a shift and insert operation is performed to shift data in the register and to insert the item into the register.
摘要翻译： 指令识别寄存器和存储器位置。 在由处理器执行指令时，从存储器位置加载一个物品，并执行移位和插入操作以移位寄存器中的数据并将该项目插入到寄存器中。
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3.发明申请System and Method of Selectively Committing a Result of an Executed Instruction 有权选择性地执行执行指令的结果的系统和方法公开(公告)号：US20090235051A1
公开(公告)日：2009-09-17
申请号：US12045825
申请日：2008-03-11
申请人： Lucian Codrescu , Robert Allan Lester , Charles Joseph Tabony , Erich James Plondke , Mao Zeng , Suresh Venkumahanti , Ajay Anant Ingle
发明人： Lucian Codrescu , Robert Allan Lester , Charles Joseph Tabony , Erich James Plondke , Mao Zeng , Suresh Venkumahanti , Ajay Anant Ingle
CPC分类号： G06F9/3853 , G06F9/30036 , G06F9/30069 , G06F9/3826 , G06F9/3828 , G06F9/3889
摘要： In a particular embodiment, a method is disclosed that includes receiving an instruction packet including a first instruction and a second instruction that is dependent on the first instruction at a processor having a plurality of parallel execution pipelines, including a first execution pipeline and a second execution pipeline. The method further includes executing in parallel at least a portion of the first instruction and at least a portion of the second instruction. The method also includes selectively committing a second result of executing the at least a portion of the second instruction with the second execution pipeline based on a first result related to execution of the first instruction with the first execution pipeline.
摘要翻译： 在特定实施例中，公开了一种方法，其包括在具有多个并行执行流水线的处理器处接收包括依赖于第一指令的第一指令和第二指令的指令分组，所述处理器包括第一执行流水线和第二执行 管道。 该方法还包括并行地执行第一指令的至少一部分和第二指令的至少一部分。 该方法还包括基于与第一执行流水线执行第一指令相关的第一结果，选择性地提交执行具有第二执行流水线的第二指令的至少一部分的第二结果。
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公开(公告)号：US20130097187A1
公开(公告)日：2013-04-18
申请号：US13275351
申请日：2011-10-18
申请人： Ajay Anant Ingle , Mao Zeng
发明人： Ajay Anant Ingle , Mao Zeng
IPC分类号： G06F17/30
CPC分类号： G06F7/492 , G06F7/24 , G06F7/36 , G06F9/30 , G06F9/30021 , G06F9/30032 , G06F9/30036
摘要： A method includes executing an instruction at a processor, where executing the instruction includes comparing a data value of a plurality of data values to a first element stored at a first location of a storage device. When the data value satisfies a condition with respect to the first element, the method includes moving the first element to a second location of the storage device and inserting the data value into the first location of the storage device.
摘要翻译： 一种方法包括在处理器处执行指令，其中执行指令包括将多个数据值的数据值与存储在存储设备的第一位置处的第一元素进行比较。 当数据值满足关于第一元素的条件时，该方法包括将第一元素移动到存储设备的第二位置，并将数据值插入存储设备的第一位置。
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公开(公告)号：US20110125987A1
公开(公告)日：2011-05-26
申请号：US12622998
申请日：2009-11-20
申请人： Erich James Plondke , Lucian Codrescu , Ajay Anant Ingle , Mao Zeng , Christopher Edward Koob , Charles Joseph Tabony
发明人： Erich James Plondke , Lucian Codrescu , Ajay Anant Ingle , Mao Zeng , Christopher Edward Koob , Charles Joseph Tabony
CPC分类号： H03M7/4006 , G06F9/30018 , G06F9/3895 , H04N19/13 , H04N19/436 , H04N19/44 , H04N19/61
摘要： A dedicated arithmetic decoding instruction is disclosed. In a particular embodiment, an apparatus includes a memory and a processor coupled to the memory. The processor is configured to execute general purpose instructions and to execute a dedicated arithmetic decoding instruction retrieved from the memory.
摘要翻译： 公开了专用算术解码指令。 在特定实施例中，装置包括存储器和耦合到存储器的处理器。 处理器被配置为执行通用指令并且执行从存储器检索的专用算术解码指令。
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公开(公告)号：US09823928B2
公开(公告)日：2017-11-21
申请号：US13249284
申请日：2011-09-30
IPC分类号： G06F9/30
CPC分类号： G06F9/3004 , G06F9/30032 , G06F9/30043
摘要： An instruction identifies a register and a memory location. Upon execution of the instruction by a processor, an item is loaded from the memory location and a shift and insert operation is performed to shift data in the register and to insert the item into the register.
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公开(公告)号：US08812516B2
公开(公告)日：2014-08-19
申请号：US13275351
申请日：2011-10-18
申请人： Ajay Anant Ingle , Mao Zeng
发明人： Ajay Anant Ingle , Mao Zeng
CPC分类号： G06F7/492 , G06F7/24 , G06F7/36 , G06F9/30 , G06F9/30021 , G06F9/30032 , G06F9/30036
摘要： A method includes executing an instruction at a processor, where executing the instruction includes comparing a data value of a plurality of data values to a first element stored at a first location of a storage device. When the data value satisfies a condition with respect to the first element, the method includes moving the first element to a second location of the storage device and inserting the data value into the first location of the storage device.
摘要翻译： 一种方法包括在处理器处执行指令，其中执行指令包括将多个数据值的数据值与存储在存储设备的第一位置处的第一元素进行比较。 当数据值满足关于第一元素的条件时，该方法包括将第一元素移动到存储设备的第二位置，并将数据值插入存储设备的第一位置。
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公开(公告)号：US08787422B2
公开(公告)日：2014-07-22
申请号：US13323917
申请日：2011-12-13
申请人： Marc M. Hoffman , Ajay Anant Ingle , Mao Zeng
发明人： Marc M. Hoffman , Ajay Anant Ingle , Mao Zeng
IPC分类号： H04B1/692
CPC分类号： G06F17/142 , G06F9/30 , G06F9/3887
摘要： A method includes executing a first instruction at a processor to perform a first fast Fourier transform (FFT) operation on a set of inputs in a time domain to produce data in a frequency domain, where the set of inputs is in a first order and where the data in the frequency domain is in a second order. The method also includes performing an operation on the data in the frequency domain to produce data in the frequency domain, where the data in the frequency domain is in the second order. The method includes executing a second instruction at the processor to perform a second FFT operation on the data in the frequency domain to produce data in the time domain, where the data in the time domain is in the first order.
摘要翻译： 一种方法包括在处理器处执行第一指令以对时域中的一组输入执行第一快速傅里叶变换（FFT）操作以产生频域中的数据，其中输入集合是第一顺序的，其中 频域中的数据是二次。 该方法还包括对频域中的数据执行操作以产生频域中的数据，其中频域中的数据是二阶。 该方法包括在处理器处执行第二指令以对频域中的数据执行第二FFT操作，以在时域中产生数据，其中时域中的数据处于第一级。
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公开(公告)号：US20130148694A1
公开(公告)日：2013-06-13
申请号：US13323917
申请日：2011-12-13
申请人： Marc M. Hoffman , Ajay Anant Ingle , Mao Zeng
发明人： Marc M. Hoffman , Ajay Anant Ingle , Mao Zeng
IPC分类号： H04B1/692
CPC分类号： G06F17/142 , G06F9/30 , G06F9/3887
摘要： A method includes executing a first instruction at a processor to perform a first fast Fourier transform (FFT) operation on a set of inputs in a time domain to produce data in a frequency domain, where the set of inputs is in a first order and where the data in the frequency domain is in a second order. The method also includes performing an operation on the data in the frequency domain to produce data in the frequency domain, where the data in the frequency domain is in the second order. The method includes executing a second instruction at the processor to perform a second FFT operation on the data in the frequency domain to produce data in the time domain, where the data in the time domain is in the first order.
摘要翻译： 一种方法包括在处理器处执行第一指令以对时域中的一组输入执行第一快速傅里叶变换（FFT）操作以产生频域中的数据，其中输入集合是第一顺序的，其中 频域中的数据是二次。 该方法还包括对频域中的数据执行操作以产生频域中的数据，其中频域中的数据是二阶。 该方法包括在处理器处执行第二指令以对频域中的数据执行第二FFT操作，以在时域中产生数据，其中时域中的数据处于第一级。
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10.发明授权公开(公告)号：US09824013B2
公开(公告)日：2017-11-21
申请号：US13466359
申请日：2012-05-08
IPC分类号： G06F12/08 , G06F12/0842 , G06F12/0846 , G06F12/0864
CPC分类号： G06F12/0842 , G06F12/0848 , G06F12/0864
摘要： Systems and methods for allocation of cache lines in a shared partitioned cache of a multi-threaded processor. A memory management unit is configured to determine attributes associated with an address for a cache entry associated with a processing thread to be allocated in the cache. A configuration register is configured to store cache allocation information based on the determined attributes. A partitioning register is configured to store partitioning information for partitioning the cache into two or more portions. The cache entry is allocated into one of the portions of the cache based on the configuration register and the partitioning register.
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