公开(公告)号：US5014191A

公开(公告)日：1991-05-07

申请号：US189189

申请日：1988-05-02

申请人： Ajay J. Padgaonkar ,  Sumit K. Mitra

发明人： Ajay J. Padgaonkar ,  Sumit K. Mitra

IPC分类号： G06F21/00

CPC分类号： G06F21/79 ,  G06F21/74 ,  G06F2221/2105

摘要： The processor executes programs from an internal EEPROM or from an external source. The EEPROM can be read either by a special operating (test) mode of the processor or by an instruction executing under normal operating mode from the EEPROM or from an external source. Similarly, the EEPROM can be programmed (written) either by a special operating mode or by under a normal operating mode instruction. The read and write circuits for the EEPROM are controlled to provide two levels of security against piracy of programmed information. In the first level, access is prevented for the read and write test modes and also for the read and write normal operating instructions if the instructions originate from an external source. In the second level, program execution from external source is also disabled.

摘要翻译： 处理器从内部EEPROM或外部源执行程序。 EEPROM可以通过处理器的特殊操作（测试）模式或通过从EEPROM或外部源在正常工作模式下执行的指令来读取。 类似地，EEPROM可以通过特殊操作模式或正常工作模式指令进行编程（写入）。 控制EEPROM的读和写电路，以提供两级安全性，防止编程信息的盗版。 在第一级中，如果指令源于外部源，则可以访问读取和写入测试模式以及读取和写入正常操作指令。 在第二级，外部源程序执行也被禁用。

公开(公告)号：US5212780A

公开(公告)日：1993-05-18

申请号：US191983

申请日：1988-05-09

申请人： Ajay J. Padgaonkar ,  Sumit K. Mitra

发明人： Ajay J. Padgaonkar ,  Sumit K. Mitra

IPC分类号： G06F5/01 ,  G11C7/10

CPC分类号： G06F5/01 ,  G11C7/1006

摘要： The RAM includes sub-arrays having odd and even memory locations, respectively. A data move instruction results in externally generated row and column address signals which are decoded to cause a first memory location, in one of the sub-arrays, to be selected and data to be read. The next memory location in sequence, in the other of the sub-arrays, is then selected, without necessity for an additional set of row address signals, for writing of the read information. The row decoder includes row indexing circuitry actuatable upon receipt of a shift signal signifying that the first memory location is in the last column of a given row. When the shift signal is received, the write location is automatically selected to be in the succeeding row.

摘要翻译： RAM包括分别具有奇数和偶数存储器位置的子阵列。 数据移动指令导致外部产生的行和列地址信号，其被解码以引起在其中一个子阵列中的第一存储器位置和要读取的数据。 然后，在另一个子阵列中顺序地选择下一个存储器位置，而不需要额外的行地址信号组来写入读取的信息。 行解码器包括在接收到表示第一存储器位置在给定行的最后一列中的移位信号时可操作的行索引电路。 当接收到移位信号时，自动选择写入位置在后面的行中。

公开(公告)号：US5426759A

公开(公告)日：1995-06-20

申请号：US973319

申请日：1992-11-09

申请人： Ajay J. Padgaonkar

发明人： Ajay J. Padgaonkar

IPC分类号： G06F9/24 ,  G06F9/26 ,  G06F11/36 ,  G06F12/12

CPC分类号： G06F9/24 ,  G06F9/26

摘要： A processor fabricated in a semiconductor chip has on-chip program memory and access to off-chip program memory. Switching between the on-chip memory and the off-chip memory is effected in the course of program execution, without using a pin-out of the device package in which the processor is housed or encapsulated, by writing a system configuration bit stored in a memory location shared by the on-chip and off-chip memories to a "1" or a "0" according to whether the program instruction is to be executed from the on-chip memory or the off-chip memory.

摘要翻译： 以半导体芯片制造的处理器具有片上程序存储器和对片外程序存储器的访问。 片上存储器和片外存储器之间的切换是在程序执行过程中进行的，而不需要通过写入存储在存储器中的系统配置位来使用处理器被封装或封装的器件封装的引脚。 根据片上存储器或片外存储器是否执行程序指令，由片上存储器和片外存储器共享的存储器位置为“1”或“0”。

公开(公告)号：US5033025A

公开(公告)日：1991-07-16

申请号：US454137

申请日：1989-12-21

申请人： Ajay J. Padgaonkar

发明人： Ajay J. Padgaonkar

IPC分类号： G11C7/10 ,  G11C7/20

CPC分类号： G11C7/1084 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/20

摘要： A semiconductor integrated circuit device has an on-chip processor and at least one on-chip digital register for storing plural bits therein. The bit contents of the register are written, selectively transformed, and read out of the register during processing of data by the processor and related circuitry. Peripheral instructions such as those from an interrupt source may contend with instructions from the processor for setting and clearing one or more bits in the register. To permit setting and clearing a unique bit in the register without affecting other bits in the register or the capability of the contending source to perform its instructions on one or more of these other bits, three separate addresses are provided for bit set, bit clear, and direct write of the register.

摘要翻译： 半导体集成电路器件具有片上处理器和用于在其中存储多个位的至少一个片上数字寄存器。 在由处理器和相关电路处理数据期间，寄存器的位内容被写入，选择性地变换和从寄存器中读出。 来自中断源的外设指令可以与来自处理器的指令相抵触，用于设置和清除寄存器中的一个或多个位。 为了允许设置和清除寄存器中的唯一位，而不影响寄存器中的其他位或竞争源在其中一个或多个位上执行其指令的能力，为位置1，位清零提供三个单独的地址， 并直接写入寄存器。