公开(公告)号：US08361870B2

公开(公告)日：2013-01-29

申请号：US12843350

申请日：2010-07-26

Applicant: Indradeep Sen ,  Thorsten Kammler ,  Andreas Knorr ,  Akif Sultan

Inventor： Indradeep Sen ,  Thorsten Kammler ,  Andreas Knorr ,  Akif Sultan

IPC: H01L21/336

CPC classification number: H01L29/78 ,  H01L21/28097 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/66606

Abstract: A semiconductor device is formed with low resistivity self aligned silicide contacts with high-K/metal gates. Embodiments include postponing silicidation of a metal layer on source/drain regions in a silicon substrate until deposition of a high-K dielectric, thereby preserving the physical and morphological properties of the silicide film and improving device performance. An embodiment includes forming a replaceable gate electrode on a silicon-containing substrate, forming source/drain regions, forming a metal layer on the source/drain regions, forming an ILD over the metal layer on the substrate, removing the replaceable gate electrode, thereby forming a cavity, depositing a high-K dielectric layer in the cavity at a temperature sufficient to initiate a silicidation reaction between the metal layer and underlying silicon, and forming a metal gate electrode on the high-K dielectric layer.

Abstract translation: 半导体器件形成为具有高K /金属栅极的低电阻率自对准硅化物接触。 实施例包括在硅衬底的源极/漏极区域上延迟金属层的硅化物，直到沉积高K电介质，从而保持硅化物膜的物理和形态特性并提高器件性能。 一个实施例包括在含硅衬底上形成可替换的栅电极，形成源极/漏极区域，在源极/漏极区域上形成金属层，在衬底上的金属层上形成ILD，去除可更换的栅电极，由此 形成空腔，在足以在金属层和下层硅之间引发硅化反应的温度下在腔中沉积高K电介质层，以及在高K电介质层上形成金属栅电极。

公开(公告)号：US08426278B2

公开(公告)日：2013-04-23

申请号：US12797420

申请日：2010-06-09

Applicant: Akif Sultan ,  Indradeep Sen

Inventor： Akif Sultan ,  Indradeep Sen

IPC: H01L21/00

CPC classification number: H01L27/088 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66636 ,  H01L29/7848

Abstract: Apparatus for semiconductor device structures and related fabrication methods are provided. A method for fabricating a semiconductor device structure on an isolated region of semiconductor material comprises forming a plurality of gate structures overlying the isolated region of semiconductor material and masking edge portions of the isolated region of semiconductor material. While the edge portions are masked, the fabrication method continues by forming recesses between gate structures of the plurality of gate structures and forming stressor regions in the recesses. The method continues by unmasking the edge portions and implanting ions of a conductivity-determining impurity type into the stressor regions and the edge portions.

Abstract translation: 提供了半导体器件结构和相关制造方法的装置。 在半导体材料的隔离区域上制造半导体器件结构的方法包括形成覆盖半导体材料的隔离区域和掩蔽半导体材料的隔离区域的边缘部分的多个栅极结构。 当边缘部分被掩蔽时，制造方法通过在多个栅极结构的栅极结构之间形成凹槽并在凹部中形成应力区域来继续。 该方法继续通过揭开边缘部分并将导电性确定杂质类型的离子注入到应力区域和边缘部分中。

公开(公告)号：US08779529B2

公开(公告)日：2014-07-15

申请号：US13692369

申请日：2012-12-03

Applicant: Indradeep Sen ,  Thorsten Kammler ,  Andreas Knorr ,  Akif Sultan

Inventor： Indradeep Sen ,  Thorsten Kammler ,  Andreas Knorr ,  Akif Sultan

IPC: H01L21/02

CPC classification number: H01L29/78 ,  H01L21/28097 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/66606

Abstract: A semiconductor device is formed with low resistivity self aligned silicide contacts with high-K/metal gates. Embodiments include postponing silicidation of a metal layer on source/drain regions in a silicon substrate until deposition of a high-K dielectric, thereby preserving the physical and morphological properties of the silicide film and improving device performance. An embodiment includes forming a replaceable gate electrode on a silicon-containing substrate, forming source/drain regions, forming a metal layer on the source/drain regions, forming an ILD over the metal layer on the substrate, removing the replaceable gate electrode, thereby forming a cavity, depositing a high-K dielectric layer in the cavity at a temperature sufficient to initiate a silicidation reaction between the metal layer and underlying silicon, and forming a metal gate electrode on the high-K dielectric layer.

Abstract translation: 半导体器件形成为具有高K /金属栅极的低电阻率自对准硅化物接触。 实施例包括在硅衬底的源极/漏极区域上延迟金属层的硅化物，直到沉积高K电介质，从而保持硅化物膜的物理和形态特性并提高器件性能。 一个实施例包括在含硅衬底上形成可替换的栅电极，形成源极/漏极区域，在源极/漏极区域上形成金属层，在衬底上的金属层上形成ILD，去除可更换的栅电极，由此 形成空腔，在足以在金属层和下层硅之间引发硅化反应的温度下在腔中沉积高K电介质层，以及在高K电介质层上形成金属栅电极。

公开(公告)号：US20120018816A1

公开(公告)日：2012-01-26

申请号：US12843350

申请日：2010-07-26

Applicant: Indradeep Sen ,  Thorsten Kammler ,  Andreas Knorr ,  Akif Sultan

Inventor： Indradeep Sen ,  Thorsten Kammler ,  Andreas Knorr ,  Akif Sultan

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/78 ,  H01L21/28097 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/66606

Abstract: A semiconductor device is formed with low resistivity self aligned silicide contacts with high-K/metal gates. Embodiments include postponing silicidation of a metal layer on source/drain regions in a silicon substrate until deposition of a high-K dielectric, thereby preserving the physical and morphological properties of the silicide film and improving device performance. An embodiment includes forming a replaceable gate electrode on a silicon-containing substrate, forming source/drain regions, forming a metal layer on the source/drain regions, forming an ILD over the metal layer on the substrate, removing the replaceable gate electrode, thereby forming a cavity, depositing a high-K dielectric layer in the cavity at a temperature sufficient to initiate a silicidation reaction between the metal layer and underlying silicon, and forming a metal gate electrode on the high-K dielectric layer.

Abstract translation: 半导体器件形成为具有高K /金属栅极的低电阻率自对准硅化物接触。 实施例包括在硅衬底的源极/漏极区域上延迟金属层的硅化物，直到沉积高K电介质，从而保持硅化物膜的物理和形态特性并提高器件性能。 一个实施例包括在含硅衬底上形成可替换的栅电极，形成源极/漏极区域，在源极/漏极区域上形成金属层，在衬底上的金属层上形成ILD，去除可更换的栅电极，由此 形成空腔，在足以在金属层和下层硅之间引发硅化反应的温度下在腔中沉积高K电介质层，以及在高K电介质层上形成金属栅电极。