公开(公告)号：US08361870B2

公开(公告)日：2013-01-29

申请号：US12843350

申请日：2010-07-26

Applicant: Indradeep Sen ,  Thorsten Kammler ,  Andreas Knorr ,  Akif Sultan

Inventor： Indradeep Sen ,  Thorsten Kammler ,  Andreas Knorr ,  Akif Sultan

IPC: H01L21/336

CPC classification number: H01L29/78 ,  H01L21/28097 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/66606

Abstract: A semiconductor device is formed with low resistivity self aligned silicide contacts with high-K/metal gates. Embodiments include postponing silicidation of a metal layer on source/drain regions in a silicon substrate until deposition of a high-K dielectric, thereby preserving the physical and morphological properties of the silicide film and improving device performance. An embodiment includes forming a replaceable gate electrode on a silicon-containing substrate, forming source/drain regions, forming a metal layer on the source/drain regions, forming an ILD over the metal layer on the substrate, removing the replaceable gate electrode, thereby forming a cavity, depositing a high-K dielectric layer in the cavity at a temperature sufficient to initiate a silicidation reaction between the metal layer and underlying silicon, and forming a metal gate electrode on the high-K dielectric layer.

Abstract translation: 半导体器件形成为具有高K /金属栅极的低电阻率自对准硅化物接触。 实施例包括在硅衬底的源极/漏极区域上延迟金属层的硅化物，直到沉积高K电介质，从而保持硅化物膜的物理和形态特性并提高器件性能。 一个实施例包括在含硅衬底上形成可替换的栅电极，形成源极/漏极区域，在源极/漏极区域上形成金属层，在衬底上的金属层上形成ILD，去除可更换的栅电极，由此 形成空腔，在足以在金属层和下层硅之间引发硅化反应的温度下在腔中沉积高K电介质层，以及在高K电介质层上形成金属栅电极。

公开(公告)号：US20120003802A1

公开(公告)日：2012-01-05

申请号：US13230083

申请日：2011-09-12

Applicant: Jian Chen ,  James F. Buller ,  Akif Sultan

Inventor： Jian Chen ,  James F. Buller ,  Akif Sultan

IPC: H01L21/336

CPC classification number: H01L29/78618 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/7848

Abstract: The present invention is directed to a transistor with an asymmetric silicon germanium source region, and various methods of making same. In one illustrative embodiment, the transistor includes a gate electrode formed above a semiconducting substrate comprised of silicon, a doped source region comprising a region of epitaxially grown silicon that is doped with germanium formed in the semiconducting substrate and a doped drain region formed in the semiconducting substrate.

Abstract translation: 本发明涉及具有不对称硅锗源区的晶体管及其制造方法。 在一个说明性实施例中，晶体管包括形成在由硅构成的半导体衬底之上的栅电极，掺杂源区包括在半导体衬底中形成的锗掺杂的外延生长硅的区域和形成在半导体衬底中的掺杂漏极区 基质。

公开(公告)号：US08035098B1

公开(公告)日：2011-10-11

申请号：US11278618

申请日：2006-04-04

Applicant: Jian Chen ,  James F. Buller ,  Akif Sultan

Inventor： Jian Chen ,  James F. Buller ,  Akif Sultan

IPC: H01L29/06 ,  H01L21/336

CPC classification number: H01L29/78618 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/7848

Abstract: The present invention is directed to a transistor with an asymmetric silicon germanium source region, and various methods of making same. In one illustrative embodiment, the transistor includes a gate electrode formed above a semiconducting substrate comprised of silicon, a doped source region comprising a region of epitaxially grown silicon that is doped with germanium formed in the semiconducting substrate and a doped drain region formed in the semiconducting substrate.

Abstract translation: 本发明涉及具有不对称硅锗源区的晶体管及其制造方法。 在一个说明性实施例中，晶体管包括形成在由硅构成的半导体衬底之上的栅电极，掺杂源区包括在半导体衬底中形成的锗掺杂的外延生长硅的区域和形成在半导体衬底中的掺杂漏极区 基质。

公开(公告)号：US07793240B2

公开(公告)日：2010-09-07

申请号：US11537390

申请日：2006-09-29

Applicant: Akif Sultan ,  Jian Chen ,  Mark W. Michael ,  Jingrong R. Zhou

Inventor： Akif Sultan ,  Jian Chen ,  Mark W. Michael ,  Jingrong R. Zhou

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: A method includes receiving design data associated with an integrated circuit device. The integrated circuit device includes a first element having a corner defined therein and a second element overlapping the first element. A dimension specified for the first element in the design data is adjusted based on a distance between the second element and the corner. The integrated circuit device is simulated based on the adjusted dimension.

Abstract translation: 一种方法包括接收与集成电路装置相关联的设计数据。 集成电路装置包括具有限定在其中的角部的第一元件和与第一元件重叠的第二元件。 基于第二元件和拐角之间的距离来调整为设计数据中的第一元件指定的尺寸。 基于经调整的尺寸模拟集成电路器件。

公开(公告)号：US07633103B2

公开(公告)日：2009-12-15

申请号：US11846318

申请日：2007-08-28

Applicant: Akif Sultan ,  James F. Buller ,  Kaveri Mathur

Inventor： Akif Sultan ,  James F. Buller ,  Kaveri Mathur

IPC: H01L29/76

CPC classification number: H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/7843

Abstract: A semiconductor device is provided which includes a substrate including an inactive region and an active region, a gate electrode structure having portions overlying the active region, a compressive layer overlying the active region, and a tensile layer overlying the inactive region and located outside the active region. The active region has a lateral edge which defines a width of the active region, and a transverse edge which defines a length of the active region. The gate electrode structure includes: a common portion spaced apart from the active region; a plurality of gate electrode finger portions integral with the common portion, and a plurality of fillet portions integral with the common portion and the gate electrode finger portions. A portion of each gate electrode finger portion overlies the active region. The fillet portions are disposed between the common portion and the gate electrode finger portions, and do not overlie the active region. The compressive layer also overlies the gate electrode finger portions, and the tensile layer is disposed adjacent the transverse edge of the active region.

Abstract translation: 提供了一种半导体器件，其包括：基板，其包括非活性区域和有源区域;栅极电极结构，其具有覆盖有源区域的部分;覆盖有源区域的压缩层;以及覆盖非活性区域并位于有源区域外部的拉伸层 地区。 有源区域具有限定有源区域的宽度的横向边缘和限定有源区域的长度的横向边缘。 栅电极结构包括：与有源区间隔开的公共部分; 与公共部分成一体的多个栅极电极指部，以及与公共部分和栅电极指部分成一体的多个圆角部分。 每个栅电极指部分的一部分覆盖有源区。 圆角部分设置在公共部分和栅极电极指部分之间，并且不覆盖有源区域。 压电层也覆盖在栅极电极指部分上，并且拉伸层邻近有源区的横向边缘设置。

公开(公告)号：US20080085570A1

公开(公告)日：2008-04-10

申请号：US11538872

申请日：2006-10-05

Applicant: Akif Sultan ,  James F. Buller ,  David Donggang Wu

Inventor： Akif Sultan ,  James F. Buller ,  David Donggang Wu

IPC: H01L21/66

CPC classification number: H01L22/12 ,  H01L22/14

Abstract: A test structure includes first and second pluralities of transistors. The first plurality of transistors includes gate electrodes of a first length. The second plurality of transistors includes gate electrodes of a second length different than the first length. A channel area of the transistors in the first plurality is substantially equal to a channel area of the transistors in the second plurality. A method for using the test structure includes measuring a performance metric of the first and second pluralities of transistors. Variation in the performance metric associated with the first plurality of transistors is compared to variation in the performance metric associated with the second plurality of transistors to identify a random length variation component associated with the first plurality of transistors.

Abstract translation: 测试结构包括第一和第二多个晶体管。 第一多个晶体管包括第一长度的栅电极。 第二多个晶体管包括与第一长度不同的第二长度的栅电极。 第一多个晶体管的沟道面积基本上等于第二多个晶体管的沟道面积。 使用测试结构的方法包括测量第一和第二多个晶体管的性能度量。 将与第一多个晶体管相关联的性能度量的变化与与第二多个晶体管相关联的性能度量的变化进行比较，以识别与第一多个晶体管相关联的随机长度变化分量。

公开(公告)号：US20070298524A1

公开(公告)日：2007-12-27

申请号：US11425913

申请日：2006-06-22

Applicant: DAVID D. WU ,  Mark W. Michael ,  Akif Sultan ,  Jingrong Zhou

Inventor： DAVID D. WU ,  Mark W. Michael ,  Akif Sultan ,  Jingrong Zhou

IPC: H01L21/66 ,  G01R31/26

CPC classification number: H01L22/34 ,  G03F7/70658 ,  H01L22/12

Abstract: The present invention is directed to methods of quantifying variations resulting from manufacturing-induced corner rounding of various features, and structures for testing same. In one illustrative embodiment, the method includes forming a plurality of test structures on a semiconducting substrate, each of the test structures having at least one physical dimension that varies relative to the other of the plurality of test structures, at least some of the test structures exhibiting at least some degree of manufacturing-induced corner rounding, forming at least one reference test structure, performing at least one electrical test on the plurality of test structures and on the reference test structure to thereby produce electrical test results, and analyzing the test results to determine an impact of the manufacturing-induced corner rounding on the performance of the plurality of test structures.

Abstract translation: 本发明涉及量化由各种特征的制造引起的角舍入引起的变化的方法和用于测试相同结构的方法。 在一个说明性实施例中，该方法包括在半导体衬底上形成多个测试结构，每个测试结构具有相对于多个测试结构中的另一个变化的至少一个物理尺寸，至少一些测试结构 表现出至少一定程度的制造引起的角落四舍五入，形成至少一个参考测试结构，对多个测试结构和参考测试结构进行至少一次电测试，从而产生电测试结果，并分析测试结果 以确定制造性角落四舍五入对多个测试结构的性能的影响。

公开(公告)号：US06593623B1

公开(公告)日：2003-07-15

申请号：US09400524

申请日：1999-09-20

Applicant: Akif Sultan

Inventor： Akif Sultan

IPC: H01L2994

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L29/6656 ,  H01L29/7836

Abstract: A method of reducing an effective channel length of a lightly doped drain transistor (50), includes the steps of forming a gate electrode (52) and a gate oxide (54) over a semiconductor substrate (56) and implanting a drain region (58) of the substrate (56) with a sub-amorphous large tilt angle implant to thereby supply interstitials (62) at a location under the gate oxide (54). The method also includes forming a lightly doped drain extension region (66) in the drain region (58) of the substrate (56) and forming a drain (70) in the drain region (58) and forming a source extension region (67) and a source (72) in a source region (60) of the substrate (56). Lastly, the method includes thermally treating the substrate (56), wherein the interstitials (62) enhance a lateral diffusion (84) under the gate oxide (54) without substantially impacting a vertical diffusion (86) of the extension regions (66, 67), thereby reducing the effective channel length without an increase in a junction depth of the drain (70) and the drain extension region (66) or the source (72) and the source extension region (67).

Abstract translation: 一种降低轻掺杂漏极晶体管（50）的有效沟道长度的方法包括以下步骤：在半导体衬底（56）上形成栅电极（52）和栅极氧化物（54），并注入漏区（58） ）具有亚非晶体大倾斜角植入物，从而在栅极氧化物（54）下方的位置处提供间隙（62）。 该方法还包括在衬底（56）的漏区（58）中形成轻掺杂漏极延伸区（66），并在漏极区（58）中形成漏极（70）并形成源延伸区（67） 以及在所述基底（56）的源极区（60）中的源极（72）。 最后，该方法包括热处理衬底（56），其中间隙（62）增强栅极氧化物（54）下方的横向扩散（84），而基本上不影响延伸区域（66,67）的垂直扩散（86） ），从而降低有效沟道长度，而不会增加漏极（70）和漏极延伸区域（66）或源极（72）和源极延伸区域（67）的结深度。

公开(公告)号：US08497179B2

公开(公告)日：2013-07-30

申请号：US12684697

申请日：2010-01-08

Applicant: Akif Sultan

Inventor： Akif Sultan

IPC: H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/78

Abstract: A method of fabricating p-type metal oxide semiconductor (PMOS) transistor devices on a common substrate is presented. The method provides a first portion of semiconductor material and a second portion of semiconductor material on the common substrate. The first portion of semiconductor material and the second portion of semiconductor material are insulated from each other. The method continues by creating first PMOS transistor devices using the first portion of semiconductor material. The first PMOS transistor devices include stressor regions that impart compressive stress to channel regions of the first PMOS transistor devices. The method also creates second PMOS transistor devices using the second portion of semiconductor material. The second PMOS transistor devices do not include channel stressor regions.

Abstract translation: 提出了在公共衬底上制造p型金属氧化物半导体（PMOS）晶体管器件的方法。 该方法提供半导体材料的第一部分和半导体材料的第二部分在公共基底上。 半导体材料的第一部分和半导体材料的第二部分彼此绝缘。 该方法通过使用半导体材料的第一部分创建第一PMOS晶体管器件来继续。 第一PMOS晶体管器件包括对第一PMOS晶体管器件的沟道区赋予压应力的应力源区域。 该方法还使用半导体材料的第二部分创建第二PMOS晶体管器件。 第二PMOS晶体管器件不包括沟道应力区域。

公开(公告)号：US08426278B2

公开(公告)日：2013-04-23

申请号：US12797420

申请日：2010-06-09

Applicant: Akif Sultan ,  Indradeep Sen

Inventor： Akif Sultan ,  Indradeep Sen

IPC: H01L21/00

CPC classification number: H01L27/088 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66636 ,  H01L29/7848

Abstract: Apparatus for semiconductor device structures and related fabrication methods are provided. A method for fabricating a semiconductor device structure on an isolated region of semiconductor material comprises forming a plurality of gate structures overlying the isolated region of semiconductor material and masking edge portions of the isolated region of semiconductor material. While the edge portions are masked, the fabrication method continues by forming recesses between gate structures of the plurality of gate structures and forming stressor regions in the recesses. The method continues by unmasking the edge portions and implanting ions of a conductivity-determining impurity type into the stressor regions and the edge portions.

Abstract translation: 提供了半导体器件结构和相关制造方法的装置。 在半导体材料的隔离区域上制造半导体器件结构的方法包括形成覆盖半导体材料的隔离区域和掩蔽半导体材料的隔离区域的边缘部分的多个栅极结构。 当边缘部分被掩蔽时，制造方法通过在多个栅极结构的栅极结构之间形成凹槽并在凹部中形成应力区域来继续。 该方法继续通过揭开边缘部分并将导电性确定杂质类型的离子注入到应力区域和边缘部分中。