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    Non-volatile memory device
    1.
    发明授权
    Non-volatile memory device 失效
    非易失性存储器件

    公开(公告)号：US07005328B2

    公开(公告)日：2006-02-28

    申请号：US10939330

    申请日：2004-09-14

    申请人： Akihiko Ebina ,  Susumu Inoue

    发明人： Akihiko Ebina ,  Susumu Inoue

    IPC分类号： H01L21/82

    CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573

    摘要： A semiconductor device having memory cells. Each of the memory cells has a word gate formed over a semiconductor substrate with a first gate insulating layer interposed, an impurity layer, and first and second control gates in the shape of sidewalls. The first and second control gates adjacent to each other with the impurity layer interposed are connected to a common contact section. The common contact section includes a first contact conductive layer, a second contact conductive layer, and a pad-shaped third contact conductive layer. The third contact conductive layer is formed over the first and second contact conductive layers.

    摘要翻译： 具有存储单元的半导体器件。 每个存储单元具有形成在半导体衬底上的字栅，其中插入有第一栅极绝缘层，杂质层以及具有侧壁形状的第一和第二控制栅极。 将杂质层相互相邻的第一和第二控制栅极连接到公共接触部分。 公共接触部分包括第一接触导电层，第二接触导电层和焊盘形第三接触导电层。 第三接触导电层形成在第一和第二接触导电层上。

    Method of manufacturing semiconductor device
    2.
    发明申请
    Method of manufacturing semiconductor device 审中-公开
    制造半导体器件的方法

    公开(公告)号：US20050148138A1

    公开(公告)日：2005-07-07

    申请号：US10961767

    申请日：2004-10-07

    申请人： Takafumi Noda ,  Susumu Inoue ,  Masahiko Tsuyuki ,  Akihiko Ebina

    发明人： Takafumi Noda ,  Susumu Inoue ,  Masahiko Tsuyuki ,  Akihiko Ebina

    IPC分类号： H01L21/283 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L27/115 ,  H01L29/423 ,  H01L29/49 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/11568 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/115

    摘要： A method of manufacturing a semiconductor device that has a high-breakdown-voltage transistor, a low-voltage driving transistor and a MONOS type memory transistor includes a step of forming a stack film that includes at least an oxide silicon layer and a nitride silicon layer over a high-breakdown-voltage transistor forming region where the high-breakdown-voltage transistor is formed, a low-voltage driving transistor forming region where the low-voltage driving transistor is formed and a MONOS type memory transistor forming region where the MONOS type memory transistor is formed in a semiconductor layer, a step of removing the stack film formed in a first gate insulating layer forming region of the high-breakdown-voltage transistor and a step of forming a first gate insulating layer in the high-breakdown-voltage transistor forming region by thermal oxidation. The method also includes a step of removing the stack film formed in the low-voltage driving transistor forming region, a step of forming a second gate insulating layer in the low-voltage driving transistor forming region, a step of forming gate electrodes in the high-breakdown-voltage transistor forming region, the low-voltage driving transistor forming region and the MONOS type memory transistor forming region and a step of forming source/drain regions in the high-breakdown-voltage transistor forming region, the low-voltage driving transistor forming region and the MONOS type memory transistor forming region.

    摘要翻译： 制造具有高击穿电压晶体管，低电压驱动晶体管和MONOS型存储晶体管的半导体器件的方法包括形成至少包含氧化硅层和氮化硅层的堆叠膜的步骤 通过形成高击穿电压晶体管的高击穿电压晶体管形成区域，形成低电压驱动晶体管的低电压驱动晶体管形成区域和MONOS型存储晶体管形成区域 存储晶体管形成在半导体层中，去除形成在高击穿电压晶体管的第一栅极绝缘层形成区域中的堆叠膜的步骤和形成高击穿电压的第一栅极绝缘层的步骤 晶体管形成区域通过热氧化。 该方法还包括去除在低电压驱动晶体管形成区域中形成的叠层膜的步骤，在低电压驱动晶体管形成区域中形成第二栅极绝缘层的步骤，在高电压驱动晶体管形成区域中形成栅电极的步骤 低电压驱动晶体管形成区域和MONOS型存储晶体管形成区域，以及在高击穿电压晶体管形成区域中形成源极/漏极区域的步骤，低电压驱动晶体管形成区域 形成区域和MONOS型存储晶体管形成区域。

    Non-volatile memory device
    7.
    发明授权
    Non-volatile memory device 失效
    非易失性存储器件

    公开(公告)号：US06891271B2

    公开(公告)日：2005-05-10

    申请号：US10244627

    申请日：2002-09-17

    申请人： Akihiko Ebina ,  Susumu Inoue

    发明人： Akihiko Ebina ,  Susumu Inoue

    IPC分类号： H01L21/8247 ,  H01L21/8234 ,  H01L21/8246 ,  H01L27/088 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L23/48

    CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573

    摘要： A semiconductor device having memory cells. Each of the memory cells has a word gate formed over a semiconductor substrate with a first gate insulating layer interposed, an impurity layer, and first and second control gates in the shape of sidewalls. The first and second control gates adjacent to each other with the impurity layer interposed are connected to a common contact section. The common contact section includes a first contact conductive layer, a second contact conductive layer, and a pad-shaped third contact conductive layer. The third contact conductive layer is formed over the first and second contact conductive layers.

    摘要翻译： 具有存储单元的半导体器件。 每个存储单元具有形成在半导体衬底上的字栅，其中插入有第一栅极绝缘层，杂质层以及具有侧壁形状的第一和第二控制栅极。 将杂质层相互相邻的第一和第二控制栅极连接到公共接触部分。 公共接触部分包括第一接触导电层，第二接触导电层和焊盘形第三接触导电层。 第三接触导电层形成在第一和第二接触导电层上。

    Semiconductor device and method of manufacturing the same
    8.
    发明授权
    Semiconductor device and method of manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号：US06812520B2

    公开(公告)日：2004-11-02

    申请号：US10234197

    申请日：2002-09-05

    申请人： Akihiko Ebina ,  Susumu Inoue

    发明人： Akihiko Ebina ,  Susumu Inoue

    IPC分类号： H01L29788

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： A semiconductor device of the present invention includes memory cells. Each of the memory cells includes a word gate formed over a semiconductor substrate with a second gate insulating layer interposed therebetween, an impurity layer, and first and second control gates in the shape of sidewalls. The first and second control gates adjacent to the impurity layer interposed therebetween is connected with a common contact section. The common contact section includes a contact conductive layer, a stopper insulating layer, and a cap insulating layer. The contact conductive layer is continuous with the first and second control gates. The cap insulating layer is formed at least over the stopper insulating layer.

    摘要翻译： 本发明的半导体器件包括存储单元。 每个存储单元包括形成在半导体衬底上的字栅，其间插有第二栅极绝缘层，杂质层以及侧壁形状的第一和第二控制栅极。 与杂质层相邻的第一和第二控制栅极与公共接触部分连接。 公共接触部分包括接触导电层，阻挡绝缘层和帽绝缘层。 接触导电层与第一和第二控制栅极连续。 帽绝缘层至少形成在止动绝缘层的上方。