公开(公告)号：US6064803A

公开(公告)日：2000-05-16

申请号：US609020

申请日：1996-02-29

申请人： Akihiro Watabe ,  Eiji Miyagoshi ,  Yoshiyuki Goi ,  William Brent Wilson

发明人： Akihiro Watabe ,  Eiji Miyagoshi ,  Yoshiyuki Goi ,  William Brent Wilson

IPC分类号： G06T9/00 ,  G06F15/00 ,  G06K9/36

CPC分类号： G06T9/007

摘要： The present invention discloses an MPEG decoder for reproducing moving picture data. A first frame memory (FM0) and a second frame memory (FM1), each of which is composed of 2N slots, are provided. A third frame memory (FM2) is provided which is composed of N+4 slots. Each slot is provided with a memory capacity of eight lines. FM0 and FM1 each have a 1-frame memory capacity for storing reference frames for motion compensation. FM2, on the other hand, has a memory capacity of half a frame+32 lines for B-PICTURE interlace conversion. A slot control memory (SM) is further provided which is composed of 2N+6 words each of which stores a respective slot number of FM2. For an output section to read the slots of FM2 in the correct order, the contents of SM are updated by an control section at the time of the writing of FM2 by a decoding section.

摘要翻译： 本发明公开了一种用于再现运动图像数据的MPEG解码器。 提供由2N个时隙构成的第一帧存储器（FM0）和第二帧存储器（FM1）。 提供由N + 4个时隙组成的第三帧存储器（FM2）。 每个插槽提供八行的存储容量。 FM0和FM1每个都具有1帧存储器容量，用于存储用于运动补偿的参考帧。 另一方面，FM2对于B-PICTURE隔行转换具有半帧+ 32行的存储容量。 还提供了一个时隙控制存储器（SM），其由2N + 6个字组成，每个字存储FM2的相应时隙号。 对于以正确的顺序读取FM2的时隙的输出部分，在由解码部分写入FM2时，由控制部分更新SM的内容。

公开(公告)号：US5689254A

公开(公告)日：1997-11-18

申请号：US540763

申请日：1995-10-11

申请人： Mikio Fujiwara ,  Yoshiyuki Goi ,  Hideki Ishii

发明人： Mikio Fujiwara ,  Yoshiyuki Goi ,  Hideki Ishii

IPC分类号： G06T9/00 ,  H03M7/46 ,  H04N7/26 ,  H04N7/30 ,  H04N1/41

CPC分类号： H03M7/46 ,  H04N19/60 ,  H04N19/13 ,  H04N19/91

摘要： After all the data words stored in a first scan transform RAM are initialized to "0"s, only signed level data words are overwritten, based on zero runlength data words, on "0"s at the positions designated by zigzag scan addresses in the first scan transform RAM. Thus, while only non-zero components out of 8.times.8 components forming one block are written in the first scan transform RAM, a block stored in a second scan transform RAM is read and initialized. Further, while only non-zero components of the next block are written in the second scan transform RAM, the block stored in the first scan transform RAM is read and initialized. This achieves, in real time, highly efficient runlength decoding responsive to a picture element clock signal of high frequency.

摘要翻译： 在存储在第一扫描变换RAM中的所有数据字被初始化为“0”之后，只有符号电平数据字被覆盖，基于零游程长度数据字，在由0字节中的Z字形扫描地址指定的位置处的“0” 第一次扫描变换RAM。 因此，虽然仅在形成一个块的8×8分量中的非零分量被写入第一扫描变换RAM中，但是存储在第二扫描变换RAM中的块被读取和初始化。 此外，只有下一块的非零分量被写入第二扫描变换RAM中时，读出并初始化存储在第一扫描变换RAM中的块。 实时地实现响应于高频的像素时钟信号的高效率的长度解码。