公开(公告)号：US20080288693A1

公开(公告)日：2008-11-20

申请号：US11886326

申请日：2007-02-16

申请人： Akinari Todoroki ,  Akihiko Tamura ,  Katsuya Tanaka ,  Hiroaki Takada ,  Shinya Honda

发明人： Akinari Todoroki ,  Akihiko Tamura ,  Katsuya Tanaka ,  Hiroaki Takada ,  Shinya Honda

IPC分类号： G06F13/24

CPC分类号： G06F9/526 ,  G06F9/4812

摘要： To provide a processor capable of achieving high processing efficiency by performing the exclusive control between task processing and interrupt handling properly even in a multiprocessor. An interrupt processor that includes a plurality of unit processors, in which at least of the plurality of unit processors is capable of performing interrupt handling requested from the outside is configured such that the unit processor P1 of the unit processors P0 to P3 comprises an purge inhibit flag 106 for causing the unit processor P1 to enter a lock state where the purge of the task is being inhibited, a hardware semaphore unit 13 for inhibiting other unit processors from accessing a predetermined region in memory accessed by the unit processor P1 after the unit processor P1 is brought into the lock state, and an interrupt control unit 11 for inhibiting the interrupt processor from performing the interrupt handling during the execution of exclusive control.

摘要翻译： 为了提供能够通过在多处理器中适当地执行任务处理和中断处理之间的排他性控制来实现高处理效率的处理器。 一种包括多个单元处理器的中断处理器，其中至少多个单元处理器能够执行从外部请求的中断处理被配置为使得单元处理器P 0至P 3的单元处理器P 1包括 用于使单位处理器P1进入禁止清除任务的锁定状态的清除禁止标志106;用于禁止其他单元处理器访问由单元处理器P访问的存储器中的预定区域的硬件信号量单元13 在单元处理器P 1进入锁定状态之后的中断处理器1，以及用于在执行专用控制期间禁止中断处理器执行中断处理的中断控制单元11。

公开(公告)号：US07702836B2

公开(公告)日：2010-04-20

申请号：US11886326

申请日：2007-02-16

申请人： Akinari Todoroki ,  Akihiko Tamura ,  Katsuya Tanaka ,  Hiroaki Takada ,  Shinya Honda

发明人： Akinari Todoroki ,  Akihiko Tamura ,  Katsuya Tanaka ,  Hiroaki Takada ,  Shinya Honda

IPC分类号： G06F13/24

CPC分类号： G06F9/526 ,  G06F9/4812

摘要： To provide a processor capable of achieving high processing efficiency by performing the exclusive control between task processing and interrupt handling properly even in a multiprocessor. An interrupt processor that includes a plurality of unit processors, in which at least of the plurality of unit processors is capable of performing interrupt handling requested from the outside is configured such that the unit processor P1 of the unit processors P0 to P3 comprises an purge inhibit flag 106 for causing the unit processor P1 to enter a lock state where the purge of the task is being inhibited, a hardware semaphore unit 13 for inhibiting other unit processors from accessing a predetermined region in memory accessed by the unit processor P1 after the unit processor P1 is brought into the lock state, and an interrupt control unit 11 for inhibiting the interrupt processor from performing the interrupt handling during the execution of exclusive control.

摘要翻译： 为了提供能够通过在多处理器中适当地执行任务处理和中断处理之间的排他性控制来实现高处理效率的处理器。 一种中断处理器，其包括多个单元处理器，其中至少多个单元处理器能够执行从外部请求的中断处理，使得单元处理器P0至P3的单元处理器P1包括清除禁止 标志106，用于使单位处理器P1进入禁止任务清除的锁定状态;硬件信号量单元13，用于在单元处理器之后禁止其他单元处理器访问由单元处理器P1访问的存储器中的预定区域 P1进入锁定状态，以及中断控制单元11，用于在执行排他控制期间禁止中断处理器执行中断处理。

公开(公告)号：US07853743B2

公开(公告)日：2010-12-14

申请号：US11979341

申请日：2007-11-01

申请人： Akinari Todoroki ,  Katsuya Tanaka ,  Hiroaki Takada ,  Shinya Honda

发明人： Akinari Todoroki ,  Katsuya Tanaka ,  Hiroaki Takada ,  Shinya Honda

IPC分类号： G06F13/00 ,  G06F13/26

CPC分类号： G06F13/26

摘要： A processor includes: a plurality of processors; a process and status managing section which manages management information including information on statuses of the plurality of processors and priorities of processes being executed by the plurality of processors; a processing processor selecting section which selects one of the processors which is executing the process with a lowest priority on the basis of the management information managed by the process and status managing section; and an interrupt controlling section which transmits a requested interrupt process to the selected processor as an interrupt process request, wherein the processing processor selecting section selects the one of the processors, which is executing the process with the lowest priority, irrespective of whether each of the requested interrupt process and the processes being executed by the processors is a task process which is handled according to a predetermined schedule or an interrupt process which is handled independently of the schedule.

摘要翻译： 处理器包括：多个处理器; 处理和状态管理部分，其管理包括关于所述多个处理器的状态的信息的管理信息和由所述多个处理器执行的处理的优先级; 处理处理器选择部，其基于由处理和状态管理部管理的管理信息，选择正在执行具有最低优先级的处理的处理器之一; 以及中断控制部分，其将所请求的中断处理发送到所选择的处理器作为中断处理请求，其中处理处理器选择部分选择正在执行具有最低优先级的进程的处理器中的一个，而不管每个 请求的中断处理，并且由处理器执行的处理是根据预定时间表处理的任务处理或者独立于时间表处理的中断处理。

公开(公告)号：US20070168592A1

公开(公告)日：2007-07-19

申请号：US11651451

申请日：2007-01-10

申请人： Akinari Todoroki ,  Katsuya Tanaka

发明人： Akinari Todoroki ,  Katsuya Tanaka

IPC分类号： G06F12/14

CPC分类号： G06F9/526

摘要： A multi-processor system with a plurality of unit processors includes: a semaphore setting section for setting semaphores representing preferential right to the competing of resources to be able to be identified to correspond to each of a plurality of the resources; a semaphore request determining section for determining, whether when a first unit processor among said unit processors requests to obtain a semaphore that is set to said semaphore setting section, the request is for requesting a semaphore being obtained by the second unit processor; and an exclusive controlling section for making the request by the first unit processor wait when it is determined that said request is for requesting a semaphore being obtained, and permitting to obtain the requested semaphore when it is determined that said request is for requesting a semaphore other than the semaphore being obtained by the semaphore request determining section.

摘要翻译： 具有多个单位处理器的多处理器系统包括：信号量设置部分，用于设置代表竞争资源的优先权以便能够被识别以对应于多个资源中的每一个的信号量; 信号量请求确定部分，用于确定在所述单元处理器中的第一单元处理器是否请求获得设置到所述信号量设置部分的信号量时，所述请求是用于请求由所述第二单元处理器获得的信号量; 以及排除控制部分，用于当确定所述请求是要求所获得的信号量时，由所述第一单元处理器进行请求等待，并且当确定所述请求用于请求信号量其他时允许获得所请求的信号量 比由信号量请求确定部获得的信号量。

公开(公告)号：US07979861B2

公开(公告)日：2011-07-12

申请号：US11651471

申请日：2007-01-10

申请人： Akinari Todoroki ,  Katsuya Tanaka

发明人： Akinari Todoroki ,  Katsuya Tanaka

IPC分类号： G06F9/46 ,  G06F13/24 ,  G06F13/26

CPC分类号： G06F9/5044 ,  G06F9/4881 ,  G06F2209/483 ,  G06F2209/5021

摘要： A multi-processor system with a plurality of unit processors includes: a request accepting section for accepting a first request and a second request, wherein the first request is a request to execute a program that can be executed in any of said unit processors and the second request is a request to execute a program that can be executed only in a specified unit processor among said unit processors; and a unit processor allocating section for allocating the first request and the second request accepted by said request accepting section to said unit processors according to priority of the first request and the second request.

摘要翻译： 具有多个单位处理器的多处理器系统包括：用于接受第一请求和第二请求的请求接收部分，其中第一请求是执行可以在任何一个所述单元处理器中执行的程序的请求， 第二请求是执行只能在所述单元处理器中的指定单元处理器中执行的程序的请求; 以及单元处理器分配部分，用于根据第一请求和第二请求的优先级将所述请求接收部分接受的第一请求和第二请求分配给所述单元处理器。

公开(公告)号：US07992042B2

公开(公告)日：2011-08-02

申请号：US11651549

申请日：2007-01-10

申请人： Akinari Todoroki ,  Katsuya Tanaka

发明人： Akinari Todoroki ,  Katsuya Tanaka

IPC分类号： G09F11/00

CPC分类号： G06F11/362

摘要： A debug support device for debugging a multiprocessor configured by a plurality of unit processors a unit processor stop section realized by a plurality of the unit processors executing a program for each of the threads, and any one of the plurality of unit processors performing a process of stopping a unit processor executing a thread in which exception handling occurs together with unit processors executing other threads when the exception handling of software occurs by a break point of a part of the plurality of threads; and a debugging execution section for performing a debugging process of detecting information about a state of the plurality of unit processors stopped by the unit processor stop section.

摘要翻译： 一种调试支持设备，用于调试由多个单元处理器配置的多处理器，由多个单元处理器实现的单元处理器停止部分，所述单元处理器停止部分为每个线程执行程序，并且所述多个单元处理器中的任何一个执行处理 当所述多个线程的一部分的断点发生软件的异常处理时，停止执行线程的单元处理器，其中与执行其他线程的单元处理器一起发生异常处理; 以及调试执行部，用于执行检测由所述单位处理器停止部所停止的所述多个单位处理器的状态的信息的调试处理。

公开(公告)号：US07797515B2

公开(公告)日：2010-09-14

申请号：US11656545

申请日：2007-01-23

申请人： Akinari Todoroki ,  Katsuya Tanaka

发明人： Akinari Todoroki ,  Katsuya Tanaka

IPC分类号： G06F9/00

CPC分类号： G06F9/4812 ,  G06F9/485

摘要： A multi-processor system includes a plurality of unit processors that operate in parallel. The system includes a suspension prohibition section for, in response to a request from at least one of the unit processors, prohibiting suspension of processing only in the requesting unit processors for which prohibiting suspension has been requested. The suspension prohibition section limits the number of unit processors for which the suspension is prohibited at the same time to a certain limited number or below.

摘要翻译： 多处理器系统包括并行操作的多个单元处理器。 该系统包括一个暂停禁止部分，用于响应于来自至少一个单元处理器的请求，禁止仅在请求单元处理器中暂停处理，该请求单元处理器已经请求禁止暂停。 暂停禁止部分将同时禁止停牌的单位处理器的数量限制在一定数量以下。

公开(公告)号：US20070180163A1

公开(公告)日：2007-08-02

申请号：US11656545

申请日：2007-01-23

申请人： Akinari Todoroki ,  Katsuya Tanaka

发明人： Akinari Todoroki ,  Katsuya Tanaka

IPC分类号： G06F3/00

CPC分类号： G06F9/4812 ,  G06F9/485

摘要： A multi-processor system with a plurality of unit processors in which the unit processors can operate in parallel includes: a suspension prohibition section for, in response to a request from at least one of the unit processors, prohibiting suspension that suspends, only in the requesting unit processor, processing executed in the unit processor.

摘要翻译： 具有多个单元处理器的多处理器系统，其中单元处理器可以并行操作，包括：暂停禁止部分，用于响应于来自至少一个单元处理器的请求，禁止暂停，仅在 请求单元处理器，在单元处理器中执行的处理。

公开(公告)号：US07877753B2

公开(公告)日：2011-01-25

申请号：US11651451

申请日：2007-01-10

申请人： Akinari Todoroki ,  Katsuya Tanaka

发明人： Akinari Todoroki ,  Katsuya Tanaka

IPC分类号： G06F9/46

CPC分类号： G06F9/526

摘要： A multi-processor system with a plurality of unit processors includes: a semaphore setting section for setting semaphores representing preferential right to the competing of resources to be able to be identified to correspond to each of a plurality of the resources; a semaphore request determining section for determining, whether when a first unit processor among said unit processors requests to obtain a semaphore that is set to said semaphore setting section, the request is for requesting a semaphore being obtained by the second unit processor; and an exclusive controlling section for making the request by the first unit processor wait when it is determined that said request is for requesting a semaphore being obtained, and permitting to obtain the requested semaphore when it is determined that said request is for requesting a semaphore other than the semaphore being obtained by the semaphore request determining section.

摘要翻译： 具有多个单位处理器的多处理器系统包括：信号量设置部分，用于设置代表竞争资源的优先权以便能够被识别以对应于多个资源中的每一个的信号量; 信号量请求确定部分，用于确定在所述单元处理器中的第一单元处理器是否请求获得设置到所述信号量设置部分的信号量时，所述请求是用于请求由所述第二单元处理器获得的信号量; 以及排除控制部分，用于当确定所述请求是要求所获得的信号量时，由所述第一单元处理器进行请求等待，并且当确定所述请求用于请求信号量其他时允许获得所请求的信号量 比由信号量请求确定部获得的信号量。

公开(公告)号：US20070169126A1

公开(公告)日：2007-07-19

申请号：US11651471

申请日：2007-01-10

申请人： Akinari Todoroki ,  Katsuya Tanaka

发明人： Akinari Todoroki ,  Katsuya Tanaka

IPC分类号： G06F9/46

CPC分类号： G06F9/5044 ,  G06F9/4881 ,  G06F2209/483 ,  G06F2209/5021

摘要： A multi-processor system with a plurality of unit processors includes: a request accepting section for accepting a first request and a second request, wherein the first request is a request to execute a program that can be executed in any of said unit processors and the second request is a request to execute a program that can be executed only in a specified unit processor among said unit processors; and a unit processor allocating section for allocating the first request and the second request accepted by said request accepting section to said unit processors according to priority of the first request and the second request.

摘要翻译： 具有多个单位处理器的多处理器系统包括：用于接受第一请求和第二请求的请求接收部分，其中第一请求是执行可以在任何一个所述单元处理器中执行的程序的请求， 第二请求是执行只能在所述单元处理器中的指定单元处理器中执行的程序的请求; 以及单元处理器分配部分，用于根据第一请求和第二请求的优先级将所述请求接收部分接受的第一请求和第二请求分配给所述单元处理器。