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1.发明授权Data transmission system and method for interconnecting sending and receiving analog devices primarily through data channels 失效主要通过数据通道互连发送和接收模拟设备的数据传输系统和方法公开(公告)号：US06381253B1
公开(公告)日：2002-04-30
申请号：US09046489
申请日：1998-03-23
IPC分类号： H04L1216
CPC分类号： H04N1/00312 , H04L12/2854 , H04N1/00281 , H04N1/32005 , H04N2201/0015 , H04Q11/0471 , H04Q2213/13031 , H04Q2213/13034 , H04Q2213/1309 , H04Q2213/13106 , H04Q2213/13174 , H04Q2213/13176 , H04Q2213/13179 , H04Q2213/13199 , H04Q2213/13202 , H04Q2213/13209 , H04Q2213/13292 , H04Q2213/1332
摘要： In a system and method of setting a data communication through an Integrated Service Digital Network (ISDN) between a transmitting analog device connected to a transmitting Terminal Adapter interfacing the ISDN network, a receiving analog device is connected to a receiving Terminal Adapter interfacing the ISDN network in a data communication system wherein a plurality of transmitting analog devices are connected and transmit data to a plurality of receiving analog devices primarily through a data channel and without device identification therein.
摘要翻译： 在与连接到ISDN网络的发送终端适配器连接的发送模拟设备之间通过综合业务数字网（ISDN）设置数据通信的系统和方法中，接收模拟设备连接到接入ISDN网络的接收终端适配器 在数据通信系统中，其中多个发送模拟设备被连接，并且主要通过数据信道向多个接收模拟设备发送数据，并且其中没有设备标识。
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公开(公告)号：US20080196032A1
公开(公告)日：2008-08-14
申请号：US12109001
申请日：2008-04-24
IPC分类号： G06F9/46
CPC分类号： G06F9/30101 , G06F9/3836
摘要： A hardware device for processing the tasks of an algorithm of the type having a number of processes the execution of some of which depend on binary decisions has a plurality of task units (10, 12, 14), each of which are associated with a task defined as being either one process or one decision or one process together with a following decision. A task interconnection logic block (16) is connected to each task unit for communicating actions from a source task unit to a destination task unit. Each task unit includes a processor (18) for processing the steps of the associated task when a received action requests such a processing. A status manager (20) handles actions coming from other task units and builds actions to be sent to other task units
摘要翻译： 一种硬件设备，用于处理具有多个进程数量的处理类型的算法的任务取决于二进制决定的任务具有多个任务单元（10,12,14），每个任务单元与任务相关联 定义为一个过程或一个决策或一个过程以及以下决定。 任务互连逻辑块（16）连接到每个任务单元，用于将来自源任务单元的操作传送到目的地任务单元。 每个任务单元包括处理器（18），用于在接收的动作请求这样的处理时处理相关任务的步骤。 状态管理器（20）处理来自其他任务单元的动作，并构建要发送到其他任务单元的动作
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公开(公告)号：US07203735B1
公开(公告)日：2007-04-10
申请号：US09659649
申请日：2000-09-12
IPC分类号： G06F15/16
CPC分类号： G06F17/30194
摘要： In a remote computer, a method for providing a file comprises the steps of receiving a request for this file, identifying this file as being stored in a distant server, requesting the distance server to send the file, identifying this file as being used, and forwarding this file. Further, in a local server, a method for transferring a file from a home server comprises the steps of receiving a request for this file, this request comprising the home server identification, checking that this file is not locally stored, requesting this file to the home server, identifying the file as being locally used, and forwarding this file.
摘要翻译： 在远程计算机中，用于提供文件的方法包括以下步骤：接收对该文件的请求，将该文件识别为存储在远程服务器中，请求距离服务器发送文件，将该文件识别为使用，以及 转发此文件。 此外，在本地服务器中，用于从家庭服务器传送文件的方法包括以下步骤：接收对该文件的请求，该请求包括家庭服务器标识，检查该文件不是本地存储的，请求该文件到 家庭服务器，将文件标识为本地使用，并转发此文件。
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公开(公告)号：US07085802B1
公开(公告)日：2006-08-01
申请号：US09680798
申请日：2000-10-06
IPC分类号： G06F13/00
CPC分类号： G06F13/4059
摘要： According to the invention, a device for transferring data between two workstations connected to a network is provided. This device comprises means for distributing data among a plurality of links of the network. Preferentially, the device comprises a dual-port memory for storing the data. In a preferred embodiment, the device further comprises a high speed interface for transmitting data from a workstation to the memory, associated with each link, a low speed interface for transmitting a part of the data from the memory to this link, and a controller for monitoring the data flow between the workstation and the plurality of links, by controlling the memory and the interfaces.
摘要翻译： 根据本发明，提供了一种用于在连接到网络的两个工作站之间传送数据的设备。 该设备包括用于在网络的多个链路之间分发数据的装置。 优选地，该设备包括用于存储数据的双端口存储器。 在优选实施例中，该设备还包括用于将数据从工作站发送到与每个链路相关联的存储器的高速接口，用于将数据的一部分从存储器传输到该链路的低速接口，以及用于 通过控制存储器和接口来监视工作站和多个链路之间的数据流。
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5.发明授权Method and apparatus for processing FISU frames according to the Signalling System 7 protocol 失效根据信令系统7协议处理FISU帧的方法和装置公开(公告)号：US06219416B1
公开(公告)日：2001-04-17
申请号：US08807491
申请日：1997-02-27
IPC分类号： H04M1500
CPC分类号： H04Q3/0025 , H04Q2213/13003 , H04Q2213/13103 , H04Q2213/13174 , H04Q2213/13176 , H04Q2213/13216 , H04Q2213/13305 , H04Q2213/1332 , H04Q2213/13322
摘要： A FISU frame handler which is connected between an adapter and a SS7 low speed network. For each FISU frames transmitted or received in the adapter, an interrupt is generated to a processor located in the adapter. In order to diminish the number of processor interruptions, the FISU frames are externally processed by the FISU frame handler by discarding repeated FISU frames transmitted from the network so as to generate idle state signals to the adapter and by converting idle state signals received from the adapter into repetitive FISU frames to transmit them to the network without interrupting the processor. In order to perform both functions, the FISU frame handler comprises two dedicated hardware units which operate according to specific methods.
摘要翻译： 连接在适配器和SS7低速网络之间的FISU帧处理器。 对于在适配器中发送或接收的每个FISU帧，将向位于适配器中的处理器生成中断。 为了减少处理器中断次数，FISU帧由FISU帧处理器通过丢弃从网络发送的重复的FISU帧来进行外部处理，以便向适配器产生空闲状态信号，并通过转换从适配器接收的空闲状态信号 重复的FISU帧将其发送到网络而不中断处理器。 为了执行这两个功能，FISU帧处理器包括根据特定方法操作的两个专用硬件单元。
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公开(公告)号：US06999994B1
公开(公告)日：2006-02-14
申请号：US09606899
申请日：2000-06-29
CPC分类号： G06F9/30101 , G06F9/3836
摘要： A hardware device for processing the tasks of an algorithm of the type having a number of processes the execution of some of which depend on binary decisions has a plurality of task units (10, 12, 14), each of which are associated with a task defined as being either one process or one decision or one process together with a following decision. A task interconnection logic block (16) is connected to each task unit for communicating actions from a source task unit to a destination task unit. Each task unit includes a processor (18) for processing the steps of the associated task when a received action requests such a processing. A status manager (20) handles actions coming from other task units and builds actions to be sent to other task units.
摘要翻译： 一种硬件设备，用于处理具有多个进程数量的处理类型的算法的任务取决于二进制决定的任务具有多个任务单元（10,12,14），每个任务单元与任务相关联 定义为一个过程或一个决策或一个过程以及以下决定。 任务互连逻辑块（16）连接到每个任务单元，用于将来自源任务单元的操作传送到目的地任务单元。 每个任务单元包括处理器（18），用于在接收的动作请求这样的处理时处理相关任务的步骤。 状态管理器（20）处理来自其他任务单元的动作，并构建要发送到其他任务单元的动作。
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7.发明授权公开(公告)号：US06961337B2
公开(公告)日：2005-11-01
申请号：US09753921
申请日：2001-01-03
IPC分类号： H04L12/701 , H04L12/741 , H04L12/773 , H04L12/28
CPC分类号： H04L45/60 , H04L45/00 , H04L45/54 , Y10S707/99933
摘要： A system and method for performing interleaved packet processing. A packet includes a source address bit pattern and a destination address bit pattern that are processed by a task processor in accordance with a data tree. A first bank of registers is utilized to load an instruction to be executed by the task processor at nodes of the data tree in accordance with the source address bit pattern. A second bank of registers is utilized for loading an instruction to be executed by the task processor at nodes of the data tree in accordance with the destination address bit pattern. A task scheduler enables the first bank of registers to transfer an instruction loaded therein for processing by the task processor only during even time cycles and for enabling the second bank of registers to transfer an instruction loaded therein for processing by the task processor only during odd time cycles.
摘要翻译： 一种用于执行交织分组处理的系统和方法。 分组包括根据数据树由任务处理器处理的源地址位模式和目的地地址位模式。 根据源地址位模式，第一组寄存器被用来加载任务处理器在数据树的节点执行的指令。 第二组寄存器用于根据目的地地址位模式将在任务处理器执行的指令加载到数据树的节点处。 任务调度器使得第一组寄存器仅在偶数时间周期期间传送加载在其中以供任务处理器处理的指令，并且仅允许第二组寄存器在奇数时间内传送其中加载的指令以供任务处理器处理 周期。
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公开(公告)号：US06725302B1
公开(公告)日：2004-04-20
申请号：US09656583
申请日：2000-09-06
IPC分类号： G06F1314
CPC分类号： G06F13/385 , G06F13/4045 , G06F2213/3814 , G06F2213/4002
摘要： The invention relates to a Universal Serial Bus (USB) with two wireless communication hubs (USB hubs). One of these hubs is connected to a first host computer, and both USB hubs are connected to a plurality of I/O devices. Each USB hub includes a wireless adapter and an antenna connected to the wireless adapter. The wireless adapter of each USB hub comprises a transmitting/receiving unit for transmitting data via the antenna to the wireless adapter of the other USB hub or receiving data via the antenna from the wireless adapter of the other USB hub. The wireless adapter also comprises a wireless dual port, which is automatically configured upstream or downstream when the first host computer is connected to one of the USB hubs.
摘要翻译： 本发明涉及具有两个无线通信集线器（USB集线器）的通用串行总线（USB）。 这些集线器中的一个连接到第一主机，并且两个USB集线器连接到多个I / O设备。 每个USB集线器包括无线适配器和连接到无线适配器的天线。 每个USB集线器的无线适配器包括用于经由天线将数据发送到另一个USB集线器的无线适配器的发送/接收单元，或者通过另一USB集线器的无线适配器经天线接收数据。 无线适配器还包括无线双端口，其在第一主机连接到其中一个USB集线器时被自动配置为上游或下游。
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9.发明授权Hardware device for parallel processing of any instruction within a set of instructions 有权用于并行处理一组指令内的任何指令的硬件设备公开(公告)号：US06675291B1
公开(公告)日：2004-01-06
申请号：US09558792
申请日：2000-04-26
IPC分类号： G06F944
CPC分类号： G06F9/38 , G06F9/30145 , G06F9/3822
摘要： Hardware device for parallel processing a determined instruction of a set of instructions having a same format defining operand fields and other data fields, the execution of this determined instruction being represented as an algorithm comprising a plurality of processes, the processing of which depending on decisions. Such a device comprises means (22-30) for activating the processing of one or several processes (32-38) determined by the operand fields of the instruction, decision macroblocks (12-20) each being associated with a specific instruction of the set of instructions, only one decision marcoblock being selected by the determined instruction in order to determine which are the process(es) to be activated for executing the determined instruction.
摘要翻译： 用于并行处理具有定义操作数字段和其他数据字段的相同格式的一组指令的确定指令的硬件设备，该确定的指令的执行被表示为包括多个处理的算法，其根据决定进行处理。 这种设备包括用于激活由指令的操作数字段确定的一个或几个处理（32-38）的处理的装置（22-30），每个与组的特定指令相关联的决策宏块（12-20） 的指令，所确定的指令仅选择一个决策marcoblock，以便确定哪些是要激活的进程来执行所确定的指令。
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公开(公告)号：US06341132B1
公开(公告)日：2002-01-22
申请号：US09018742
申请日：1998-02-04
IPC分类号： H04L1256
CPC分类号： H04Q11/0478 , H04L2012/5647 , H04L2012/5652
摘要： A telecommunication node for an Asynchronous Transfer Mode (ATM) telecommunication network performs Segmentation and Reassembly (SAR) of ATM cells. The SAR particularly provides Virtual Channel Identifier (VCI) and Virtual Path Identifier (VPI) translation and further provides a Direct Memory Access (DMA) for accessing an external storage. When the VCI and VPI identifiers are representative of an Error Code Correcting (ECC) procedure to be carried out in the local mode, the SAR circuit performs a first DMA access which is decoded by an address decoder. Conversely, when no ECC procedure is locally required, the SAR decodes the VCI and VPI and performs a second DMA access which is also decoded by the address decoder. The latter decoding is then used by a Reed-Solomon Coder and Decoder for possibly performing an error correcting procedure on the ATM message formed by the ATM cells being processed.
摘要翻译： 用于异步传输模式（ATM）电信网络的电信节点执行ATM信元的分段和重组（SAR）。 SAR特别提供虚拟信道标识符（VCI）和虚拟路径标识符（VPI）转换，并进一步提供用于访问外部存储器的直接存储器访问（DMA）。 当VCI和VPI标识符代表在本地模式下执行的错误代码校正（ECC）过程时，SAR电路执行由地址解码器解码的第一DMA访问。 相反，当本地不需要ECC过程时，SAR对VCI和VPI进行解码，并执行也被地址解码器解码的第二DMA访问。 后来的解码然后由Reed-Solomon编码器和解码器用于可能对正被处理的ATM信元形成的ATM信息执行纠错过程。
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