公开(公告)号：US6038656A

公开(公告)日：2000-03-14

申请号：US151334

申请日：1998-09-11

申请人： Alain J. Martin ,  Andrew M. Lines ,  Uri V. Cummings

发明人： Alain J. Martin ,  Andrew M. Lines ,  Uri V. Cummings

IPC分类号： G06F15/78 ,  G06F15/00

CPC分类号： G06F15/8053

摘要： An asynchronous circuit having a pipelined completion mechanism to achieve improved throughput.

摘要翻译： 具有流水线完成机制以实现提高吞吐量的异步电路。

公开(公告)号：US06502180B1

公开(公告)日：2002-12-31

申请号：US09496128

申请日：2000-02-01

申请人： Alain J. Martin ,  Andrew M. Lines ,  Uri V. Cummings

发明人： Alain J. Martin ,  Andrew M. Lines ,  Uri V. Cummings

IPC分类号： G06F1582

CPC分类号： G06F15/8053 ,  G06F9/3871

摘要： An asynchronous circuit having a pipelined completion mechanism to achieve improved throughput.

摘要翻译： 具有流水线完成机制以实现提高吞吐量的异步电路

公开(公告)号：US07934031B2

公开(公告)日：2011-04-26

申请号：US11433203

申请日：2006-05-11

申请人： Andrew M. Lines ,  Alain J. Martin ,  Uri Cummings

发明人： Andrew M. Lines ,  Alain J. Martin ,  Uri Cummings

IPC分类号： G06F13/00 ,  G06F15/76 ,  H03K19/00 ,  H03K19/173 ,  G11C7/10

CPC分类号： G06F7/00 ,  G06F9/3869

摘要： An asynchronous logic family of circuits which communicate on delay-insensitive flow-controlled channels with 4-phase handshakes and 1 of N encoding, compute output data directly from input data using domino logic, and use the state-holding ability of the domino logic to implement pipelining without additional latches.

摘要翻译： 一个异步逻辑系列电路，通过四相握手的延迟不敏感的流量控制通道和N个编码的1个，使用多米诺逻辑直接从输入数据计算输出数据，并使用多米诺逻辑的状态保持能力 实现流水线，无需附加锁存器。

公开(公告)号：US20180174040A1

公开(公告)日：2018-06-21

申请号：US15385219

申请日：2016-12-20

申请人： Michael I. Davies ,  Andrew M. Lines

发明人： Michael I. Davies ,  Andrew M. Lines

IPC分类号： G06N3/08 ,  G06N3/063

CPC分类号： G06N3/08 ,  G06N3/049 ,  G06N3/063

摘要： A neuromorphic computing apparatus has a network of neuromorphic cores, with each core including an input axon and a plurality of neurons having synapses. The input axon is associated with an input data store to store an input trace representing a time series of filtered pre-synaptic spike events, and accessible by the synapses of the plurality of neurons of the core. Each neuron includes at least one dendritic compartment to store and process variables representing a dynamic state of the neuron. Each compartment is associated with a compartment-specific data store to store an output trace representing a time series of filtered post-synaptic spike events. Each neuron includes a learning engine to apply a set of one or more learning rules based on the pre-synaptic and post-synaptic spike events to produce an adjustment of parameters of a corresponding synapse to those spike events.