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    Simultaneously formed isolation trench and through-box contact for silicon-on-insulator technology
    3.
    发明授权
    Simultaneously formed isolation trench and through-box contact for silicon-on-insulator technology 有权
    同时形成隔离沟槽和绝缘体上硅技术的通孔接触

    公开(公告)号：US08021943B2

    公开(公告)日：2011-09-20

    申请号：US12625701

    申请日：2009-11-25

    申请人： Alan B. Botula ,  BethAnn Rainey ,  Daniel S. Vanslette

    发明人： Alan B. Botula ,  BethAnn Rainey ,  Daniel S. Vanslette

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/743 ,  H01L21/76224 ,  H01L21/76232

    摘要： A semiconductor fabrication method comprises providing a structure which includes a semiconductor substrate having a plurality of subsurface layers, the substrate comprising a top surface and the subsurface layers comprising a top subsurface layer below the top surface of the substrate. A protective material is patterned on the top surface of the device and a material removal process is performed to simultaneously form a contact trench and an isolation trench, the material removal process removing at least a portion of the top surface and the top subsurface layer such that the contact trench and the isolation trench are formed within the subsurface layer. An insulator is then formed within the isolation trench and the contact trench is lined with the insulator. The contact trench is then filled with a conductive material such that the conductive material is deposited over the insulator.

    摘要翻译： 半导体制造方法包括提供包括具有多个次表面层的半导体衬底的结构，所述衬底包括顶表面，并且所述表面下层包括在所述衬底的顶表面下方的顶部表面层。 保护材料被图案化在器件的顶表面上，并且执行材料去除工艺以同时形成接触沟槽和隔离沟槽，所述材料去除工艺去除顶表面和顶部表面下层的至少一部分，使得 接触沟槽和隔离沟槽形成在地下层内。 然后在隔离沟槽内形成绝缘体，并且接触沟槽衬有绝缘体。 然后用导电材料填充接触沟槽，使得导电材料沉积在绝缘体上。

    SIMULTANEOUSLY FORMED ISOLATION TRENCH AND THROUGH-BOX CONTACT FOR SILICON-ON-INSULATOR TECHNOLOGY
    4.
    发明申请
    SIMULTANEOUSLY FORMED ISOLATION TRENCH AND THROUGH-BOX CONTACT FOR SILICON-ON-INSULATOR TECHNOLOGY 有权
    同时形成的隔离开关和通孔盒接触硅绝缘子技术

    公开(公告)号：US20110124177A1

    公开(公告)日：2011-05-26

    申请号：US12625701

    申请日：2009-11-25

    申请人： Alan B. Botula ,  BethAnn Rainey ,  Daniel S. Vanslette

    发明人： Alan B. Botula ,  BethAnn Rainey ,  Daniel S. Vanslette

    IPC分类号： H01L21/762 ,  H01L21/768

    CPC分类号： H01L21/743 ,  H01L21/76224 ,  H01L21/76232

    摘要： A semiconductor fabrication method comprises providing a structure which includes a semiconductor substrate having a plurality of subsurface layers, the substrate comprising a top surface and the subsurface layers comprising a top subsurface layer below the top surface of the substrate. A protective material is patterned on the top surface of the device and a material removal process is performed to simultaneously form a contact trench and an isolation trench, the material removal process removing at least a portion of the top surface and the top subsurface layer such that the contact trench and the isolation trench are formed within the subsurface layer. An insulator is then formed within the isolation trench and the contact trench is lined with the insulator. The contact trench is then filled with a conductive material such that the conductive material is deposited over the insulator.

    摘要翻译： 半导体制造方法包括提供包括具有多个次表面层的半导体衬底的结构，所述衬底包括顶表面，并且所述表面下层包括在所述衬底的顶表面下方的顶部表面层。 保护材料被图案化在器件的顶表面上，并且执行材料去除工艺以同时形成接触沟槽和隔离沟槽，所述材料去除工艺去除顶表面和顶部表面下层的至少一部分，使得 接触沟槽和隔离沟槽形成在地下层内。 然后在隔离沟槽内形成绝缘体，并且接触沟槽衬有绝缘体。 然后用导电材料填充接触沟槽，使得导电材料沉积在绝缘体上。

    finFET TRANSISTOR AND CIRCUIT
    5.
    发明申请
    finFET TRANSISTOR AND CIRCUIT 有权
    finFET晶体管和电路

    公开(公告)号：US20100203689A1

    公开(公告)日：2010-08-12

    申请号：US12762427

    申请日：2010-04-19

    申请人： Kerry Bernstein ,  Edward J. Nowak ,  BethAnn Rainey

    发明人： Kerry Bernstein ,  Edward J. Nowak ,  BethAnn Rainey

    IPC分类号： H01L21/336

    CPC分类号： H01L29/785 ,  H01L29/045 ,  H01L29/66795

    摘要： A drive strength tunable FinFET, a method of drive strength tuning a FinFET, a drive strength ratio tuned FinFET circuit and a method of drive strength tuning a FinFET, wherein the FinFET has either at least one perpendicular and at least one angled fin or has at least one double-gated fin and one split-gated fin.

    摘要翻译： 驱动强度可调谐FinFET，FinFET的驱动强度调谐方法，驱动强度比调谐FinFET电路和FinFET的驱动强度调谐方法，其中FinFET具有至少一个垂直和至少一个成角度的鳍或具有 最少一个双门翅和一个分闸门。

    DESIGN STRUCTURES INCLUDING MEANS FOR LATERAL CURRENT CARRYING CAPABILITY IMPROVEMENT IN SEMICONDUCTOR DEVICES
    6.
    发明申请
    DESIGN STRUCTURES INCLUDING MEANS FOR LATERAL CURRENT CARRYING CAPABILITY IMPROVEMENT IN SEMICONDUCTOR DEVICES 有权
    设计结构包括用于半导体器件中的横向电流承载能力改进的手段

    公开(公告)号：US20090106726A1

    公开(公告)日：2009-04-23

    申请号：US11873711

    申请日：2007-10-17

    申请人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

    发明人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

    IPC分类号： G06F17/50

    CPC分类号： H01L21/76816 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A design structure including a semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.

    摘要翻译： 包括半导体结构的设计结构。 半导体结构包括（a）基板; （b）基板上的第一半导体器件; （c）第一半导体器件上的N ILD（层间电介质）层，其中N是大于1的整数; 和（d）电耦合到第一半导体器件的导电线。 导电线适于在平行于N个ILD层的两个连续ILD层之间的界面表面的横向方向上承载横向电流。 导电线路存在于N ILD层的至少两个ILD层中。 导电线不包括适于在垂直于接口表面的垂直方向承载垂直电流的导电通孔。

    METHODS FOR LATERAL CURRENT CARRYING CAPABILITY IMPROVEMENT IN SEMICONDUCTOR DEVICES
    7.
    发明申请
    METHODS FOR LATERAL CURRENT CARRYING CAPABILITY IMPROVEMENT IN SEMICONDUCTOR DEVICES 失效
    用于半导体器件中的横向电流承载能力改进的方法

    公开(公告)号：US20080122096A1

    公开(公告)日：2008-05-29

    申请号：US11460314

    申请日：2006-07-27

    申请人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

    发明人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

    IPC分类号： H01L23/52 ,  H01L21/4763

    CPC分类号： H01L21/76838 ,  H01L21/8249 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/53295 ,  H01L27/0623 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor structure and methods for forming the same. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.

    摘要翻译： 半导体结构及其形成方法。 半导体结构包括（a）基板; （b）基板上的第一半导体器件; （c）第一半导体器件上的N ILD（层间电介质）层，其中N是大于1的整数; 和（d）电耦合到第一半导体器件的导电线。 导电线适于在平行于N个ILD层的两个连续ILD层之间的界面表面的横向方向上承载横向电流。 导电线路存在于N ILD层的至少两个ILD层中。 导电线不包括适于在垂直于接口表面的垂直方向承载垂直电流的导电通孔。

    Multi-height FinFETS
    8.
    发明授权
    Multi-height FinFETS 有权
    多高度FinFETS

    公开(公告)号：US06909147B2

    公开(公告)日：2005-06-21

    申请号：US10249738

    申请日：2003-05-05

    申请人： Ingo Aller ,  Joachim Keinert ,  Thomas Ludwig ,  Edward J. Nowak ,  BethAnn Rainey

    发明人： Ingo Aller ,  Joachim Keinert ,  Thomas Ludwig ,  Edward J. Nowak ,  BethAnn Rainey

    IPC分类号： H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04 ,  H01L29/786 ,  H01L21/8238 ,  H01L29/78

    CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/66795

    摘要： The present invention provides a FinFET device that has a first fin and a second fin. Each fin has a channel region and source and drain regions that extend from the channel region. The fins have different heights. The invention has a gate conductor positioned adjacent the fins. The gate conductor runs perpendicular to the fins and crosses the channel region of each of the first fin and second fin. The fins are parallel to one another. The ratio of the height of the first fin to the height of the second fin comprises a ratio of one to 2/3. The ratio is used to tune the performance of the transistor and determines the total channel width of the transistor.

    摘要翻译： 本发明提供一种具有第一鳍片和第二鳍片的FinFET器件。 每个散热片具有从沟道区延伸的沟道区和源极和漏极区。 翅片具有不同的高度。 本发明具有邻近散热片定位的栅极导体。 栅极导体垂直于翅片延伸并与第一鳍片和第二鳍片中的每一个的沟道区域交叉。 翅片彼此平行。 第一翅片的高度与第二翅片的高度的比率为1/2/3的比例。 该比率用于调整晶体管的性能并确定晶体管的总通道宽度。

    High mobility crystalline planes in double-gate CMOS technology
    9.
    发明授权
    High mobility crystalline planes in double-gate CMOS technology 有权
    双栅极CMOS技术中的高迁移率晶面

    公开(公告)号：US06794718B2

    公开(公告)日：2004-09-21

    申请号：US10248123

    申请日：2002-12-19

    申请人： Edward J. Nowak ,  BethAnn Rainey

    发明人： Edward J. Nowak ,  BethAnn Rainey

    IPC分类号： H01L2712

    CPC分类号： H01L29/785 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0922 ,  H01L27/1211 ,  H01L29/66795 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A MOS device with first and second freestanding semiconductor bodies formed on a substrate. The first freestanding semiconductor body has a first portion thereof disposed at a non-orientation orthogonal, non parallel orientation with respect to a first portion of the second freestanding semiconductor body. These portions of said first and second freestanding semiconductor bodies have respective first and second crystalline orientations. A first gate electrode crosses over at least part of said first portion of said first freestanding semiconductor body at a non-orthogonal angle, as does a second gate electrode over the first portion of the second freestanding semiconductor body.

    摘要翻译： 具有形成在基板上的第一和第二独立半导体本体的MOS器件。 第一独立半导体本体具有相对于第二独立半导体本体的第一部分以非正交的非平行取向设置的第一部分。 所述第一和第二独立半导体本体的这些部分具有相应的第一和第二晶体取向。 第一栅电极与第二独立半导体本体的第一部分上的第二栅电极非正交角度交叉​​在所述第一独立半导体本体的所述第一部分的至少一部分上。

    Virtual body-contacted trigate
    10.
    发明授权
    Virtual body-contacted trigate 失效
    虚拟身体接触的三位一体

    公开(公告)号：US07700446B2

    公开(公告)日：2010-04-20

    申请号：US11830868

    申请日：2007-07-31

    申请人： Brent A. Anderson ,  Matthew J. Breitwisch ,  Edward J. Nowak ,  BethAnn Rainey

    发明人： Brent A. Anderson ,  Matthew J. Breitwisch ,  Edward J. Nowak ,  BethAnn Rainey

    IPC分类号： H01L21/336

    CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78615 ,  H01L29/78687

    摘要： A field effect transistor (FET) and method of forming the FET comprises a substrate; a silicon germanium (SiGe) layer over the substrate; a semiconductor layer over and adjacent to the SiGe layer; an insulating layer adjacent to the substrate, the SiGe layer, and the semiconductor layer; a pair of first gate structures adjacent to the insulating layer; and a second gate structure over the insulating layer. Preferably, the insulating layer is adjacent to a side surface of the SiGe layer and an upper surface of the semiconductor layer, a lower surface of the semiconductor layer, and a side surface of the semiconductor layer. Preferably, the SiGe layer comprises carbon. Preferably, the pair of first gate structures are substantially transverse to the second gate structure. Additionally, the pair of first gate structures are preferably encapsulated by the insulating layer.

    摘要翻译： 场效应晶体管（FET）和形成FET的方法包括：衬底; 衬底上的硅锗（SiGe）层; 在SiGe层上并邻近SiGe层的半导体层; 与衬底相邻的绝缘层，SiGe层和半导体层; 邻近绝缘层的一对第一栅极结构; 以及绝缘层上的第二栅极结构。 优选地，绝缘层与SiGe层的侧表面，半导体层的上表面，半导体层的下表面和半导体层的侧表面相邻。 优选地，SiGe层包含碳。 优选地，该对第一栅极结构基本上横向于第二栅极结构。 此外，该对第一栅极结构优选地被绝缘层封装。