公开(公告)号：US20090106726A1

公开(公告)日：2009-04-23

申请号：US11873711

申请日：2007-10-17

申请人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

发明人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

IPC分类号： G06F17/50

CPC分类号： H01L21/76816 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： A design structure including a semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.

摘要翻译： 包括半导体结构的设计结构。 半导体结构包括（a）基板; （b）基板上的第一半导体器件; （c）第一半导体器件上的N ILD（层间电介质）层，其中N是大于1的整数; 和（d）电耦合到第一半导体器件的导电线。 导电线适于在平行于N个ILD层的两个连续ILD层之间的界面表面的横向方向上承载横向电流。 导电线路存在于N ILD层的至少两个ILD层中。 导电线不包括适于在垂直于接口表面的垂直方向承载垂直电流的导电通孔。

公开(公告)号：US20080122096A1

公开(公告)日：2008-05-29

申请号：US11460314

申请日：2006-07-27

申请人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

发明人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L21/76838 ,  H01L21/8249 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/53295 ,  H01L27/0623 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure and methods for forming the same. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.

摘要翻译： 半导体结构及其形成方法。 半导体结构包括（a）基板; （b）基板上的第一半导体器件; （c）第一半导体器件上的N ILD（层间电介质）层，其中N是大于1的整数; 和（d）电耦合到第一半导体器件的导电线。 导电线适于在平行于N个ILD层的两个连续ILD层之间的界面表面的横向方向上承载横向电流。 导电线路存在于N ILD层的至少两个ILD层中。 导电线不包括适于在垂直于接口表面的垂直方向承载垂直电流的导电通孔。

公开(公告)号：US07453151B2

公开(公告)日：2008-11-18

申请号：US11460314

申请日：2006-07-27

申请人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

发明人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

IPC分类号： H01L29/80

CPC分类号： H01L21/76838 ,  H01L21/8249 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/53295 ,  H01L27/0623 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure and methods for forming the same. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.

摘要翻译： 半导体结构及其形成方法。 半导体结构包括（a）基板; （b）基板上的第一半导体器件; （c）第一半导体器件上的N ILD（层间电介质）层，其中N是大于1的整数; 和（d）电耦合到第一半导体器件的导电线。 导电线适于在平行于N个ILD层的两个连续ILD层之间的界面表面的横向方向上承载横向电流。 导电线路存在于N ILD层的至少两个ILD层中。 导电线不包括适于在垂直于接口表面的垂直方向承载垂直电流的导电通孔。

公开(公告)号：US07904868B2

公开(公告)日：2011-03-08

申请号：US11873711

申请日：2007-10-17

申请人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

发明人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

IPC分类号： G06F17/50

CPC分类号： H01L21/76816 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： A design structure including a semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.

摘要翻译： 包括半导体结构的设计结构。 半导体结构包括（a）衬底; （b）基板上的第一半导体器件; （c）第一半导体器件上的N ILD（层间电介质）层，其中N是大于1的整数; 和（d）电耦合到第一半导体器件的导电线。 导电线适于在平行于N个ILD层的两个连续ILD层之间的界面表面的横向方向上承载横向电流。 导电线路存在于N ILD层的至少两个ILD层中。 导电线不包括适于在垂直于接口表面的垂直方向承载垂直电流的导电通孔。

公开(公告)号：US20080308940A1

公开(公告)日：2008-12-18

申请号：US12198196

申请日：2008-08-26

申请人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

发明人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

IPC分类号： H01L23/522

CPC分类号： H01L21/76838 ,  H01L21/8249 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/53295 ,  H01L27/0623 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.

摘要翻译： 半导体结构。 半导体结构包括（a）基板; （b）基板上的第一半导体器件; （c）第一半导体器件上的N ILD（层间电介质）层，其中N是大于1的整数; 和（d）电耦合到第一半导体器件的导电线。 导电线适于在平行于N个ILD层的两个连续ILD层之间的界面表面的横向方向上承载横向电流。 导电线路存在于N ILD层的至少两个ILD层中。 导电线不包括适于在垂直于接口表面的垂直方向承载垂直电流的导电通孔。

公开(公告)号：US20100210043A1

公开(公告)日：2010-08-19

申请号：US12371724

申请日：2009-02-16

申请人： Qizhi Liu ,  Ping-Chuan Wang ,  Kimball M. Watson ,  Zhijian J. Yang

发明人： Qizhi Liu ,  Ping-Chuan Wang ,  Kimball M. Watson ,  Zhijian J. Yang

IPC分类号： H01L21/66 ,  G06F19/00

CPC分类号： H01L22/34 ,  H01L2924/3011

摘要： A system, method and device for measuring a depth of a Through-Silicon-Via (TSV) in a semiconductor device region on a wafer during in-line semiconductor fabrication, includes a resistance measurement trench structure having length and width dimensions in a substrate, ohmic contacts on a surface of the substrate disposed on opposite sides of the resistance measurement trench structure, and an unfilled TSV structure in semiconductor device region having an unknown depth. A testing circuit makes contact with the ohmic contacts and measures a resistance therebetween, and a processor connected to the testing circuit calculates a depth of the trench structure and the unfilled TSV structure based on the resistance measurement. The resistance measurement trench structure and the unfilled TSV are created simultaneously during fabrication.

摘要翻译： 在线半导体制造期间，用于测量晶片上的半导体器件区域中的硅硅通孔（TSV）的深度的系统，方法和装置包括在衬底中具有长度和宽度尺寸的电阻测量沟槽结构， 设置在电阻测量沟槽结构的相对侧的衬底的表面上的欧姆接触，以及具有未知深度的半导体器件区域中的未填充的TSV结构。 测试电路与欧姆接触件接触并测量它们之间的电阻，连接到测试电路的处理器基于电阻测量来计算沟槽结构的深度和未填充的TSV结构。 在制造期间同时产生电阻测量沟槽结构和未填充TSV。

公开(公告)号：US07904273B2

公开(公告)日：2011-03-08

申请号：US12371724

申请日：2009-02-16

申请人： Qizhi Liu ,  Ping-Chuan Wang ,  Kimball M. Watson ,  Zhijian J. Yang

发明人： Qizhi Liu ,  Ping-Chuan Wang ,  Kimball M. Watson ,  Zhijian J. Yang

IPC分类号： G06F19/00

CPC分类号： H01L22/34 ,  H01L2924/3011

摘要： A system, method and device for measuring a depth of a Through-Silicon-Via (TSV) in a semiconductor device region on a wafer during in-line semiconductor fabrication, includes a resistance measurement trench structure having length and width dimensions in a substrate, ohmic contacts on a surface of the substrate disposed on opposite sides of the resistance measurement trench structure, and an unfilled TSV structure in semiconductor device region having an unknown depth. A testing circuit makes contact with the ohmic contacts and measures a resistance therebetween, and a processor connected to the testing circuit calculates a depth of the trench structure and the unfilled TSV structure based on the resistance measurement. The resistance measurement trench structure and the unfilled TSV are created simultaneously during fabrication.

摘要翻译： 在线半导体制造期间，用于测量晶片上的半导体器件区域中的硅硅通孔（TSV）的深度的系统，方法和装置包括在衬底中具有长度和宽度尺寸的电阻测量沟槽结构， 设置在电阻测量沟槽结构的相对侧的衬底的表面上的欧姆接触，以及具有未知深度的半导体器件区域中的未填充的TSV结构。 测试电路与欧姆接触件接触并测量它们之间的电阻，连接到测试电路的处理器基于电阻测量来计算沟槽结构的深度和未填充的TSV结构。 在制造期间同时产生电阻测量沟槽结构和未填充TSV。

公开(公告)号：US07701015B2

公开(公告)日：2010-04-20

申请号：US10596573

申请日：2003-12-16

申请人： Zhong-Xiang He ,  Bradley A. Orner ,  Vidhya Ramachandran ,  Alvin J. Joseph ,  Stephen A. St. Onge ,  Ping-Chuan Wang

发明人： Zhong-Xiang He ,  Bradley A. Orner ,  Vidhya Ramachandran ,  Alvin J. Joseph ,  Stephen A. St. Onge ,  Ping-Chuan Wang

IPC分类号： H01L29/72

CPC分类号： H01L21/76838 ,  H01L21/76802 ,  H01L21/8249 ,  H01L23/485 ,  H01L23/5389 ,  H01L27/0623 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a method and structure for an integrated circuit structure that includes a plurality of complementary metal oxide semiconductor (CMOS) transistors and a plurality of vertical bipolar transistors positioned on a single substrate. The vertical bipolar transistors are taller devices than the CMOS transistors. In this structure, a passivating layer is positioned above the substrate, and between the vertical bipolar transistors and the CMOS transistors. A wiring layer is above the passivating layer. The vertical bipolar transistors are in direct contact with the wiring layer and the CMOS transistors are connected to the wiring layer by contacts extending through the passivating layer.

摘要翻译： 公开了一种集成电路结构的方法和结构，其包括多个互补金属氧化物半导体（CMOS）晶体管和位于单个衬底上的多个垂直双极晶体管。 垂直双极晶体管比CMOS晶体管更高的器件。 在该结构中，钝化层位于衬底上方，并且位于垂直双极晶体管和CMOS晶体管之间。 布线层位于钝化层的上方。 垂直双极晶体管与布线层直接接触，并且CMOS晶体管通过延伸穿过钝化层的触点连接到布线层。

公开(公告)号：US20090283840A1

公开(公告)日：2009-11-19

申请号：US12119526

申请日：2008-05-13

申请人： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Ephrem G. Gebreselasie ,  Zhong-Xiang He ,  Herbert Lei Ho ,  Deok-kee Kim ,  Chandrasekharan Kothandaraman ,  Dan Moy ,  Robert Mark Rassel ,  John Matthew Safran ,  Kenneth Jay Stein ,  Norman Whitelaw Robson ,  Ping-Chuan Wang ,  Hongwen Yan

发明人： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Ephrem G. Gebreselasie ,  Zhong-Xiang He ,  Herbert Lei Ho ,  Deok-kee Kim ,  Chandrasekharan Kothandaraman ,  Dan Moy ,  Robert Mark Rassel ,  John Matthew Safran ,  Kenneth Jay Stein ,  Norman Whitelaw Robson ,  Ping-Chuan Wang ,  Hongwen Yan

IPC分类号： H01L27/06 ,  H01L21/8234

CPC分类号： H01L27/0629 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least one of a fuse structure, an anti-fuse structure and a resistor structure located and formed at least in part simultaneously upon an isolation region laterally separated from the active region within the semiconductor substrate. The field effect device includes a gate dielectric comprising a high dielectric constant dielectric material and a gate electrode comprising a metal material. The at least one of the fuse structure, anti-fuse structure and resistor structure includes a pad dielectric comprising the same material as the gate dielectric, and optionally, also a fuse, anti-fuse or resistor that may comprise the same metal material as the gate electrode.

摘要翻译： 半导体结构和半导体结构的制造方法提供一种场效应器件，其位于和形成在半导体衬底的有源区上，并且至少一个熔丝结构，抗熔丝结构和电阻结构中的至少一个至少位于并形成 部分地同时地在与半导体衬底内的有源区域横向分离的隔离区域上。 场效应器件包括包括高介电常数介电材料的栅极电介质和包括金属材料的栅电极。 熔丝结构，反熔丝结构和电阻器结构中的至少一个包括包括与栅极电介质相同的材料的焊盘电介质，以及可选地还包括熔断器，反熔丝或电阻器，其可以包括与所述栅极电介质相同的金属材料 栅电极。

公开(公告)号：US08159040B2

公开(公告)日：2012-04-17

申请号：US12119526

申请日：2008-05-13

申请人： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Ephrem G. Gebreselasie ,  Zhong-Xiang He ,  Herbert Lei Ho ,  Deok-kee Kim ,  Chandrasekharan Kothandaraman ,  Dan Moy ,  Robert Mark Rassel ,  John Matthew Safran ,  Kenneth Jay Stein ,  Norman Whitelaw Robson ,  Ping-Chuan Wang ,  Hongwen Yan

发明人： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Ephrem G. Gebreselasie ,  Zhong-Xiang He ,  Herbert Lei Ho ,  Deok-kee Kim ,  Chandrasekharan Kothandaraman ,  Dan Moy ,  Robert Mark Rassel ,  John Matthew Safran ,  Kenneth Jay Stein ,  Norman Whitelaw Robson ,  Ping-Chuan Wang ,  Hongwen Yan

IPC分类号： H01L29/00

CPC分类号： H01L27/0629 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least one of a fuse structure, an anti-fuse structure and a resistor structure located and formed at least in part simultaneously upon an isolation region laterally separated from the active region within the semiconductor substrate. The field effect device includes a gate dielectric comprising a high dielectric constant dielectric material and a gate electrode comprising a metal material. The at least one of the fuse structure, anti-fuse structure and resistor structure includes a pad dielectric comprising the same material as the gate dielectric, and optionally, also a fuse, anti-fuse or resistor that may comprise the same metal material as the gate electrode.

摘要翻译： 半导体结构和半导体结构的制造方法提供一种场效应器件，其位于和形成在半导体衬底的有源区上，并且至少一个熔丝结构，抗熔丝结构和电阻结构中的至少一个至少位于并形成 部分地同时地在与半导体衬底内的有源区域横向分离的隔离区域上。 场效应器件包括包括高介电常数介电材料的栅极电介质和包括金属材料的栅电极。 熔丝结构，反熔丝结构和电阻器结构中的至少一个包括包括与栅极电介质相同的材料的焊盘电介质，以及可选地还包括熔断器，反熔丝或电阻器，其可以包括与所述栅极电介质相同的金属材料 栅电极。